CLA70000 Zarlink Semiconductor, CLA70000 Datasheet - Page 8

• Manufacturer Part Number: CLA70000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

CLA70000 Series
Encoders
ENA8T3
ENB10T4
Flip-Flop
FFA8
FFB6
FFC4
FFD8
ALU/Functional Generator
FGA5
Adders
MCA4
Multiplers
MLA10
MLB4X4
MLW7
Multiplexors
MXA8T1
MXB4T1
MXB4T1A
MXC2T1
MXC2T1A
MXD4T1
MXE4T1
MXF2T1
Parity Generator
PGA9
Shift Registers
SRA2
SRA4
SRA8
SRA8A
SRB2
SRB4
SRB8
8
8 line to 3 line priority encoder
10 line to 4 line priority encode
8 bit bistable latches
6 bit D-type flip-flop with clear
4 bit D-type flip-flop with clear &
complimentary outputs
Octal D-type flip-flop with clear
4 bit ALU/function generator
4 bit magnitude comparators
Decade rate multiplier
4 by 4 binary multiplier with tristate
outputs
7 bit Wallace trees with tristate
outputs
8 line to 1 line data selector /
multiplexer
Dual 4 line to 1 line data selector /
multiplexers
Dual 4 line to 1 line data selector /
multiplexer with inverted tristate
outputs
Quad 2 to 1 data selector / multiplexers
Quad 2 to 1 selector (inverted outputs)
4 to 1 multiplexor with strobe
4 to 1 multiplexor with strobe
2 to 1 multiplexeor with storage
9 bit odd/even parity
generator/checker
2 bit POS shift register with clear
4 bit POS shift register with clear
8 bit SIPO shift register with clear
8 bit SIPO shift register without clear
2 bit PISO shift register with clear
4 bit PISO shift register with clear
2 bit PISO shift register with clear
SRB8A
SRC8
SRD4
SRE4
SRF8
SRG4
SRJ4
SRK5
Process Monitor
PERF
BIST *
RGBIT
RGTBIT
RGDIAG
RGCTL
RGHOLD
* (early built in self test cells) see CLA7BIST Library
CLA70000 Paracell Library
Memory Cells
RBRAM
ROROM
Test register (one monitor bit)
ROM MAX 65536 bits per block
Performance monitor
Test register (one bit)
Diagnostic control unit
Test register controller
Test register hold circuitry
RAM MAX 16384 bits per block
2 bit PISO shift register without clear
8 bit PISO shift register with clear
8 bit SIPO shift register with clear
4 bit PIPO shift register with JKbar
input
8 bit shift and store register with
tristate outputs
4 bit bidirectional universal shift
register
4 bit parallel access shift register
5 bit shift register
WORDS 2:128, bits 1:128 (min:max)
WORDS 2:2048, bits 2:64 (min:max)