CLA70000 Zarlink Semiconductor, CLA70000 Datasheet - Page 9

• Manufacturer Part Number: CLA70000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

Design Support and Interfaces
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available from various centers worldwide each of which is
connected to our Headquarters via high speed data links. A
design center engineer is assigned to each customer’s circuit,
to ensure good communication , and a smooth and efficient
design flow. It should be noted that sign-off simulation against
the 'golden' simulator is also supported at our local design
centers.
routes as illustrated in the table below. Differing interface
methods allow for varying levels of involvement in a manner
which complements individual customer design styles, whilst
maintaining our responsibility to ensure first time working
devices.
operates a thorough design audit procedure to verify
compliance with customer specification and to ensure
manufacturability. The procedure includes four separate
review meetings, with the customer, held at key stages of the
design.
Review 1:
Flexible design route approach
Design center engineer assigned to every customer
circuit
Full turnkey service capability
Design and layout support for CLA70000 arrays is
Zarlink Semiconductor offers a variety of formal design
As part of the design process Zarlink Semiconductor
OPTIONS
Design Review 1
Schematic Capture
Logical Design
Design Review 2
Physical Design
Design Review 3
Prototype
Manufacturing
Prototype Evaluation
Design Review 4
Production
Held at the beginning of the design cycle
THIRD PARTY
SOFTWARE
CUSTOMER
CUSTOMER
CUSTOMER
GPS
GPS
GPS
CAD SUPPORT
Design Routes
PDS IN-HOUSE
Review 2:
Review 3:
Review 4:
Design Tools
methodology is that of maintaining an open CAD system with
all interfaces standardized via EDIF 2.0 . This enables us to
provide full support for a variety of 3rd party ASIC design tools
and facilitates rapid updating of associated libraries. It also
provides an interface to the Zarlink Semiconductor (PDS2)
CUSTOMER or GPS
SOFTWARE
The focus of the Zarlink Semiconductor design tool
CUSTOMER
CUSTOMER
CUSTOMER
GPS
GPS
To check and agree on all performance,
packaging, specifications and design
timescales.
Held after Logic Simulation but prior to
Layout
Checks to ensure satisfactory functionality,
timing performance, and adequate fault
coverage.
Held after Layout and Post Layout Simulation
Verification of satisfactory design performance
after insertion of actual track loads. Final check
of all device specifications before prototype
manufacture.
Held after Prototype Delivery
Confirm that devices meet all specifications
and are suitable for full scale production.
CLA70000 Series
TURNKEY
SERVICE
CUSTOMER
GPS
GPS
GPS
GPS
GPS
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