CLA90000 Zarlink Semiconductor, CLA90000 Datasheet - Page 2

• Manufacturer Part Number: CLA90000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

Silicon and process
This generation of gate arrays uses a 0.6 µ m process and
meets its primary objectives of dense architecture and low
power without compromising performance. Packing den-
sity is 5,500 available gates per mm
three-layer metal typically exceeding 70% (random logic).
Power consumption is low with both 5V and 3V supplies,
reaching 0.5 µ W/MHz/gate at 3V with two gate loads.
Service
The service Zarlink offers to customers encompasses
product guidance from a marketing team, engineering
expertise, including design advice and in-depth knowledge
of CAE tools, through to fast delivery and world class qual-
ity and reliability standards.
ARRAY SIZES
CLA90000 consists of a series of fixed, embedded and
optimized arrays that can be combined as shown below.
Standard, fixed array sizes are prefabricated and appropri-
ate probe cards are available for fast turn around and low
cost.
For a design with a large memory (2k bits or more) or
when an embedded macro like an ARM RISC micropro-
cessor is required, all device layers can be fabricated. An
embedded array uses the fixed array bases but with a sec-
tion of the array removed to make space for the custom
block. Optimized arrays are customized to the application,
can be built with the required number of pads or gates, and
can also include embedded cells.
Optimized arrays are most often used in medium- to high-
volume applications where the larger engineering cost is
balanced by lower production pricing. For high volume
devices, an optimized array can be generated at Zarlink
using automated tools. The Zarlink Design Centres can
advise on the best options, in terms of fixed gate arrays
and standard cells, for a given design.
Embedded and optimized arrays are as easy to design
with as the fixed array bases, and have similar prototyping
times provided custom cell definition or new array size is
decided early in the design.
2
Fixed arrays
Embedded
memory or
macros
2
, with utilization for
Optimized arrays
A wide range of packages is offered for both the fixed and
optimized arrays, and all arrays offer the choice of com-
mercial or military pad density. The lower pad density
meets the need of MIL STD customers in terms of bond
wire spacing specifications.
CLA90000 has a range of fixed array bases to offer a suit-
able array size for most applications, from low to high vol-
ume.
Fixed Gate Arrays
Optimized Gate Arrays
* optimized arrays available up to 1.1M gates.
# MIL density pad spacing
Array
CLA 901
CLA 902
CLA 903
CLA 904
CLA 905
CLA 906
CLA 907
CLA 908
CLA 909
CLA 910
CLA 911
CLA 912
CLA 913
CLA 914
Array
*CLA9XX
No. of
Gates
21632
32768
57800
75272
95048
141512
168200
228488
262088
297992
336200
376712
419528
512072
Max.
No. of
Gates
114912
8
Typical Utilization
of Gates
2-layer
metal
Typical Utilization
of Gates
2-layer
metal
517000
102000
117000
134000
151000
169000
188000
230000
14000
26000
33000
42000
63000
75000
9700
3-layer
metal
3-layer
metal
804000
117000
160000
183000
208000
235000
263000
293000
358000
15000
23000
40000
52000
66000
99000
Number of
Pads
84
100
128
144
160
192
208
240
256
272
288
304
320
352
Max. Number
of Pads
520
44
52
64
72
80
96
104
120
128
136
144
152
160
176
264