CLA90000 Zarlink Semiconductor, CLA90000 Datasheet - Page 3

• Manufacturer Part Number: CLA90000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

Choosing an Array
To find the most suitable array for an application, refer to
the array table on the left and find the smallest one that
has enough pads, remembering to look at the correct pad
density column and to include power and ground pads. If
the array has enough gates, the design is ‘pad limited’, and
will have spare gates. If the design needs more gates, and
therefore a bigger array, it is ‘gate limited’ and will have
spare pads.
An additional consideration is the number of I/O pins that
can be tested by automatic test equipment. The locally
based Zarlink Design Centre will help resolve any testing
issues.
If a design is pad limited, it requires the smallest array with
sufficient pads. Two-layer metal (CLA prefix) is generally
the most economical. If the selection process arrives at a
gate limited design, it requires the smallest array with suffi-
cient usable gates and three-layer metal (CLT prefix) will
generally be lower cost. Also, if a special clock or power
distribution scheme is required, three layer metal is often
needed.
ARCHITECTURE
I Compact routable core cell
I Typical design reduced in silicon area by up to 50% over
I Utilization from 45% to 80% for triple-layer metal,
I Efficient register file RAM (3 gates/bit)
I Custom full layer (embedded) RAM option for larger
The gate array core cell was chosen after researching a
number of different cell layouts. The core cell contains four
transistors, two NMOS and two PMOS. These are built as
one structure with a shared central source/drain region
with the polysilicon gates independently available. This
core cell layout gives efficient metal interconnections for a
range of logic gates, flip-flops, and register file RAM, and
also permits over-cell routing to increase gate utilization.
the previous gate array generation
depending on design topology
memories
I/O ARRANGEMENT
I I/O cell options for 3V and 5V supply
I 3V and 5V I/O on the same device
I Slew rate control on outputs
I Excellent ESD protection to 3kV and good latch-up
I PCI /PC Card fully compatible I/Os
A wide range of I/O cells is available, and each one has
three forms to suit 3V, 5V, or mixed 3 and 5V operation.
Also, each I/O cell can be individually configured as one of
the following:
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The I/O stage has a number of components used to con-
struct a wide variety of I/O cells, including pullup and pull-
down resistors and small transistors for oscillators. 5V
cells are available with TTL or CMOS compatible input
Schmitt circuitry. 3V cells meet both TTL and CMOS spec-
ifications.
The CLA90000 has four separate internal supply rails: one
for the core, one for the buffer, and two for output areas of
the chip. The buffer supply rail is completely isolated for
very low noise. This offers the benefit of good noise immu-
nity with multiple supply voltage capability to suit the appli-
cation. The mixed 3 and 5V I/O capability can be used for
power saving or interfacing with 3V and 5V systems.
Slew rate control is provided within the I/O output drive cir-
cuitry to minimize switching noise transients. This is a use-
ful feature in larger designs, particularly where multiple
high drive outputs switch simultaneously. It also reduces
reflections from unterminated pc board tracks.
Electrostatic discharge (ESD) protection is built into the
input and output cells, and has been designed to withstand
in excess of 3kV (human body model). The structure and
process is also highly resistant to latch-up and able to
withstand forward bias currents in excess of 200mA.
immunity to 200mA, meets STACK 0001 V12.1 and MIL
STD 883
Input
Output
Tristate output
Open drain output
Open source output
Bidirectional
Open drain bidirectional
Open source bidirectional
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