MT9044AL1 Zarlink Semiconductor, Inc., MT9044AL1 Datasheet - Page 16

• Manufacturer Part Number: MT9044AL1
• Description: Dual Reference Frequency Selectable Digital PLL with Multiple Clock Outputs for T1/E1 (ITU-T G.812 type IV), Stratum (3, 4, 4E) and STS-3/OC3 Systems
• Manufacturer: Zarlink Semiconductor, Inc.

MT9044
CTS CXO-65-HG-5-C-20.0MHz
Frequency:
Tolerance:
Rise & Fall Time:
Duty Cycle:
The output clock should be connected directly (not
AC coupled) to the OSCi input of the MT9044, and
the OSCo output should be left open as shown in
Figure 9.
Crystal
Oscillator may be used. A complete oscillator circuit
made up of a crystal, resistor and capacitors is
shown in Figure 10.
The accuracy of a crystal oscillator depends on the
crystal tolerance as well as the load capacitance
tolerance. Typically, for a 20MHz crystal specified
with a 32pF load capacitance, each 1pF change in
load capacitance contributes approximately 9ppm to
the frequency deviation. Consequently, capacitor
tolerances, and stray capacitances have a major
effect on the accuracy of the oscillator frequency.
The trimmer capacitor shown in Figure 10 may be
used to compensate for capacitive effects. If
accuracy is not a concern, then the trimmer may be
removed, the 39pF capacitor may be increased to
56pF, and a wider tolerance crystal may be
substituted.
The crystal should be a fundamental mode type - not
an overtone. The fundamental mode crystal permits
a simpler oscillator circuit with no additional filter
components and is less likely to generate spurious
responses. The crystal specification is as follows.
Frequency:
Tolerance:
Oscillation Mode:
16
1uH inductor: may improve stability and is optional
MT9044
Figure 10 - Crystal Oscillator Circuit
Oscillator
OSCo
OSCi
1MΩ
-
56pF
20MHz
25ppm 0C to 70C
8ns (0.5V 4.5V 50pF)
45% to 55%
Alternatively,
100Ω
20MHz
20MHz
As required
Fundamental
39pF
1uH
a
3-50pF
Crystal
Resonance Mode:
Load Capacitance:
Maximum Series Resistance:
Approximate Drive Level:
e.g., CTS R1027-2BB-20.0MHZ
(
Guard Time Adjustment
Excessive switching of the timing reference (from
PRI to SEC) in the MT9044 can be minimized by first
entering
maximum time (i.e., guard time). If the degraded
signal returns to normal before the expiry of the
guard time (e.g. 2.5 seconds), then the MT9044 is
returned to its Normal Mode (with no reference
switch taking place). Otherwise, the reference input
may be changed from Primary to Secondary.
A simple way to control the guard time (using
Automatic Control) is with an RC circuit as shown in
Figure 11. Resistor R
limits the current flowing into the GTi pin during
power down conditions. The guard time can be
calculated as follows.
•
In cases where fast toggling might be expected of
the LOS1 input, then an unsymmetrical Guard Time
Circuit is recommended. This ensures that reference
switching doesn’t occur until the full guard time value
±
20ppm absolute,
V
Schmitt Trigger input, see DC Electrical
Characteristics
SIH
Figure 11 - Symmetrical Guard Time Circuit
MT9044
is the logic high going threshold level for the GTi
guard time
guard time RC 0.6
example
guard time 150k 10u
Holdover
GTo
GTi
±
6ppm 0C to 50C, 32pF, 25
≈
≈
=
Mode
150kΩ
RC
P
R
×
is for protection only and
×
×
ln
1kΩ
R
for



P
--------------------------------
V DD V SIH
Parallel
32pF
35
1mW
×
Ω
+
0.6
a
V DD
10uF
–
=
C
predetermined
0.9s
Ω



)