MT9044AL1 Zarlink Semiconductor, Inc., MT9044AL1 Datasheet - Page 17

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MT9044AL1

Manufacturer Part Number
MT9044AL1
Description
Dual Reference Frequency Selectable Digital PLL with Multiple Clock Outputs for T1/E1 (ITU-T G.812 type IV), Stratum (3, 4, 4E) and STS-3/OC3 Systems
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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has expired. An unsymmetrical Guard Time Circuit is
shown in Figure 12.
Figure 13 shows a typical timing example of an
unsymmetrical Guard Time Circuit with the MT9044
in Automatic Control.
TIE Correction (using GTi)
When Primary Holdover Mode is entered for short
time periods, TIE correction should not be enabled.
This will prevent unwanted accumulated phase
change between the input and output. This is mainly
applicable to Manual Control, since Automatic
Control together with the Guard Time Circuit
inherently operate in this manner.
NOTES:
1. T
bad to when the MT9044 is provided with a LOS indication.
MT9044
D
MT9044
Figure 12 - Unsymmetrical Guard Time
STATE
STATUS
STATUS
SIGNAL
SIGNAL
represents the time delay from when the reference goes
SEC
PRI
LOS2
LOS1
GTo
GTi
Figure 13 - Automatic Control, Unsymmetrical Guard Time Circuit Timing Example
GTo
GTi
V
150kΩ
NORMAL
1kΩ
SIH
R
R
GOOD
PRI
C
D
Circuit
1kΩ
R
P
HOLDOVER
T
BAD
D
PRI
10uF
C
+
NORMAL
GOOD
PRI
GOOD
For instance, 10 Normal to Holdover to Normal mode
change sequences occur, and in each case Holdover
was entered for 2s. Each mode change sequence
could account for a phase change as large as 350ns.
Thus, the accumulated phase change could be as
large as 3.5us, and, the overall MTIE could be as
large as 3.5us.
When 10 Normal to Holdover to Normal mode
change sequences occur without MTIE enabled, and
in each case holdover was entered for 2s, each
mode change sequence could still account for a
phase change as large as 350ns. However, there
would be no accumulated phase change, since the
input to output phase is re-aligned after every
Holdover to Normal state change. The overall MTIE
would only be 350ns.
HOLDOVER
T
D
0.05ppm is the accuracy of Holdover Mode
50ns is the maximum phase continuity of the
MT9044 from Normal Mode to Holdover Mode
200ns is the maximum phase continuity of the
MT9044 from Holdover Mode to Normal Mode (with
or without TIE Corrector Circuit)
PRI
Phase hold
Phase state
Phase 10
BAD
=
=
10
=
NORMAL
0.05ppm 2s
50ns
×
SEC
(
250ns
+
200ns
×
+
100ns
=
=
NORMAL
250ns
100ns
GOOD
)
PRI
MT9044
=
3.5us
17

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