MT90502 Zarlink Semiconductor, Inc., MT90502 Datasheet

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MT90502

Manufacturer Part Number
MT90502
Description
Multi-Channel AAL2 SAR
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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Part Number:
MT90502AG
Quantity:
60
Features
4096 x64 Kbps
AAL2 Segmentation Reassembly device
capable of simultaneously processing up to
1023 active CIDs (AAL2 Channel Identifier) and
1023 active VCC (Virtual Channel
Connections).
ATM VCCs can support up to 255 CIDs.
Implements AAL2 Common Part Sub-layer
(CPS) functions specified in ITU I.363.2.
CPS packet payload can support up to 64
bytes.
Can support over-subscription of 10:1.
TDM Bus supports Multiple Data Transfer
formats such as ITU G.711, G.726, G.723,
G.728 and G.729.
Support for a DSP array to perform a variety of
operations such as compression of voice.
Interface to DSP is by means of bit and byte
aligned HDLC encoding on the TDM interface.
Two UTOPIA ports: Ports A & B are
configurable as a single 8-bit UTOPIA Level 2
PHY Port with 5 ADDR lines or dual 8-bit
UTOPIA Level 1 configurable as PHY or ATM.
Third UTOPIA port for connection to an external
TDM Bus
Clock and
Frame
Pulse
MT90502
Generation
Recovery
SSRAM
Module
Clock
TDM
and
Memory Bank A
SDRAM
Figure 1 - MT90502 Functional Block
CPS Packet
Transmitter
CPS Packet
Receiver
Dual Memory Controller
CPU Interface
DS5420
AAL5 SAR processor, or for chaining multiple
MT90502 devices.
TDM bus provides 32 bidirectional serial TDM
streams operating at 2.40, 4.096, and 8.192
Mbits/s.
Support clock recovery and generation.
Performs silence suppression for PCM and
ADPCM.
Capability to inject and recover CPS packets
through the CPU host processor bus.
8-bit or 16-bit microprocessor port, configurable
to Motorola or Intel timing.
IEEE 1149 (JTAG) interface.
Transmitter
AAL2 SAR
AAL2 SAR
Receiver
MT90502AG
SSRAM
Memory Bank B (Optional)
Ordering Information
Multi-Channel AAL2 SAR
Preliminary Information
0 to +70 ° C
JTAG Interface
456 Pin Plastic BGA
ISSUE 1
UTOPIA
SDRAM
Module
Port
Port
Port
B
A
C
MT90502
November 2000
RxA Port
TxA Port
TxB Port
RxC Port
TxC Port
RxB Port
1

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MT90502 Summary of contents

Page 1

... SSRAM Dual Memory Controller CPS Packet AAL2 SAR Transmitter Receiver AAL2 SAR CPS Packet Transmitter Receiver CPU Interface Figure 1 - MT90502 Functional Block MT90502 Multi-Channel AAL2 SAR Preliminary Information ISSUE 1 November 2000 Ordering Information 456 Pin Plastic BGA 0 to +70 ° C SDRAM UTOPIA ...

Page 2

... UTOPIA Level 2 Multi-PHY port. Port C is UTOPIA Level 1 compliant. The MT90502 provides the capability of routing ATM cells to different UTOPIA interfaces, SAR engine or CPU. This feature can be used to connect another MT90502 (to support over 2000 phone calls connect an external AAL1 and AAL5 SAR. ...

Page 3

... Preliminary Information Figure 2 - 456 PBGA MT90502 ...

Page 4

... MT90502 Preliminary Information Pin Description EPBGA Pin Name AC3 mclk_src CPU Clock. F25, F23, cpu_mode[3:0] CPU Interface Mode Select (4 bits). The CPU Interface Mode Select bits must be J24, J23 hardwired. AA3, AA4, cpu_a[14:0] CPU Address bus. Y1, Y2, Y3, Y4, W1, W2, W3, W4, V1, ...

Page 5

... UTOPIA port C TX Cell Available (in ATM) 2. txc_enb 2. UTOPIA port C TX Enable (in PHY) E3, E2, E1, txc_d[7:0] UTOPIA port C TX Data bus F3, F2, F1, G4 txc_prty UTOPIA port C TX Parity L1 rxc_clk UTOPIA port C RX clock H3 rxc_soc UTOPIA port C RX Start of Cell Preliminary Information Description (see notes 1-8) MT90502 5 ...

Page 6

... MT90502 Preliminary Information Pin Description (continued) EPBGA Pin Name L2 1. rxc_enb 1. UTOPIA port C RX Enable (in ATM) 2. rxc_clav 2. UTOPIA port C RX Cell Available (in PHY rxc_clav 1. UTOPIA port C RX Cell Available (in ATM) 2. rxc_enb 2. UTOPIA port C RX Enable (in PHY) H1, J3, J2, rxc_d[7:0] UTOPIA port C RX Data bus ...

Page 7

... SDRAM bank B Row Address Select AF21 memb_we SDRAM bank B Write Enable AA25, AA26, memb_a[18:0] SDRAM/SSRAM bank B address bus Y23, Y24, AC21, AE20, AC19, AF20, AE19, AD19, AF19, AE18, AC17, AE17, AD16, AF17, AD17, AF18, AD18 Preliminary Information Description (see notes 1-8) MT90502 7 ...

Page 8

... E16, E19, E20, G5, G22, H5, H22, L5, L22, M5, M22, R5, R22, T5, T22, W5, W22, Y5, Y22, AB7, AB8, AB11, AB12, AB15, AB16, AB19, AB20, AC4, AC23, AD3, AD24 If MT90502 is only connected to 3.3V devices on the H.100/H.110 bus, then 3.3V can be connected to the following pins. If any devices are 5V then these pins must be connected to 5V. ...

Page 9

Pin #1 Corner 3.00*45 (4x) 20.00 REF 30 Typ. C Seating Plane Package Outlines ...

Page 10

North America - West Coast Tel: (858) 675-3400 Fax: (858) 675-3450 Tel: +65 333 6193 Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) ...

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