MT90502 Zarlink Semiconductor, Inc., MT90502 Datasheet - Page 8

• Manufacturer Part Number: MT90502
• Description: Multi-Channel AAL2 SAR
• Manufacturer: Zarlink Semiconductor, Inc.

MT90502
Pin Description (continued)
VSS (0V): D9, D11, E5, E6, E9, E10, E13, E14, E17,
E18, E21, E22, F4, F5, F22, H4, J5, J22, K5, K22,
L4, L11, L12, L13, L14, L15, L16, M4, M11, M12,
M13, M14, M15, M16, N5, N11, N12, N13, N14, N15,
N16, N22, P5, P11, P12, P13, P14, P15, P16, P22,
R11, R12, R13, R14, R15, R16, T11, T12, T13, T14,
T15, T16, U5, U22, V5, V22, AA5, AA22, AB5, AB6,
AB9, AB10, AB13, AB14, AB17, AB18, AB21, AB22
VDD3 (3.3 V): C3, C24, D23, E7, E8, E11, E12, E15,
E16, E19, E20, G5, G22, H5, H22, L5, L22, M5,
M22, R5, R22, T5, T22, W5, W22, Y5, Y22, AB7,
AB8, AB11, AB12, AB15, AB16, AB19, AB20, AC4,
AC23, AD3, AD24
If MT90502 is only connected to 3.3V devices on the
H.100/H.110 bus, then 3.3V can be connected to the
following pins. If any devices are 5V then these pins
must be connected to 5V.
VDD5 (3.3 V or 5.0 V): B25, D24, H26, L26, P25,
U24
8
AF26, AC24,
AB23, AA23,
EPBGA Pin
T24, R26,
N23, M23
AA1
AB2
AC5
AB3
AE2
AB1
AE1
A26
D22
A25
C23
A23
AF1
A5
B5
crpll_clk_o
PLLGND1
PLLGND2
PLLGND3
crpll_clk_i
PLLVDD1
PLLVDD2
PLLVDD3
gpio[7:0]
nreset
pll_clk
Name
Preliminary Information
tms
trst
tdo
tck
tdi
Global Hardware Reset
General Purpose I/Os
Test Reset (Test Pin)
Test Clock (Test Pin)
Test Data In (Test Pin)
Test Mode Select (Test Pin)
Test Data Out (Test Pin)
PLL clock used for H.100 Master clock generation
Clock Recovery PLL Output
Clock Recovery PLL Input
PLL Power Pin (3.3V)
PLL Power Pin (3.3V)
PLL Power Pin (3.3V)
PLL Ground Pin (0V)
PLL Ground Pin (0V)
PLL Ground Pin (0V)
Phase Lock Loop (PLL) Pins
Miscellaneous Pins
Test Pins
Description (see notes 1-8)
Not Connected (Leave Floating): A20, B16, B18,
B19, B23, B24, B26, C4, C5, C16, C22, C26, D16,
D19, D26, E23, H23, H25, K23, K25, L25, M26, N24,
N26, P26, R23, T23, T25, U25, V25, AA2, AB4, AC6,
AC8, AC11, AC13, AC16, AC18, AC22, AD1, AD2,
AD4, AD23, AE25, AF25
Notes:
1. All outputs are +3.3 V
2. All input and output pins that are designated (F) can
withstand 5 V
3. All input and output pins that are designated (F) are tested
with a 50 pF load unless otherwise specified.
4. Designations under the “rst” (reset condition) table column
are: X = undefined; Z = high impedance; 1 = high (+3.3 V
5. I/O types include: Output (O), Input (I), Bidirectional (I/O),
Power (PWR) and Ground (GND).
6. All buses have pins listed in order from MSB to LSB.
7. Pins with more than one function are listed under their main
(default) function.8. Unused H.100/H.110 input pins should be
tied high with an external pull-up.
8. Unused H.100/H.110 input pins should be tied high with an
external pull-up.
DC
being applied to them.
DC
.
DC
).