MT90502 Zarlink Semiconductor, Inc., MT90502 Datasheet - Page 4

• Manufacturer Part Number: MT90502
• Description: Multi-Channel AAL2 SAR
• Manufacturer: Zarlink Semiconductor, Inc.

MT90502
Pin Description
4
Y4, W1, W2,
W3, W4, V1,
N4, M1, M2,
EPBGA Pin
N1, N2, N3,
T3, R1, R2,
R3, R4, P1,
V2, V3, V4,
P2, P3, P4,
Y1, Y2, Y3,
AA3, AA4,
C15, B15,
A15, C14,
B14, A14,
F25, F23,
D13, C13
J24, J23
AC3
AC2
AC1
C21
A19
D21
D12
D14
A13
B13
D15
C12
M3
U1
U4
U3
U2
T2
T1
T4
A9
B9
cpu_rdy_ndtack Intel Ready & Motorola Data Ack.
cpu_mode[3:0] CPU Interface Mode Select (4 bits). The CPU Interface Mode Select bits must be
cpu_a[14:0]
cpu_d[15:0]
cpu_a_das
cpu_wr_rw
2. txa_clav
1. txa_clav
1. rxa_enb
2. rxa_clav
cpu_rd_ds
1. txa_enb
2. txa_enb
rxa_alarm
txa_d[7:0]
interrupt1
interrupt2
mclk_src
cpu_ale
txa_prty
rxa_soc
txa_soc
rxa_led
cpu_cs
txa_led
rxa_clk
txa_clk
Name
Preliminary Information
CPU Clock.
hardwired.
CPU Address bus.
Intel Write & Motorola Read/Write
Intel Read & Motorola Data Strobe
Address Latch Enable
Direct Access Select. ‘1’ selects the direct address space. ‘0’ selects the
indirection registers contained in the CPU interface. This pin can be connected to
the MSB of an address bus but does not behave as an address pin.
CPU chip select
CPU Data bus
Interrupt 1 (configurable polarity)
Interrupt 2 (configurable polarity)
UTOPIA port A TX LED
UTOPIA port A RX LED
UTOPIA port A PHY alarm
UTOPIA port A TX clock
UTOPIA port A TX Start of Cell
1. UTOPIA port A TX Enable (in ATM)
2. UTOPIA port A TX Cell Available (in PHY)
1. UTOPIA port A TX Cell Available (in ATM)
2. UTOPIA port A TX Enable (in PHY)
UTOPIA port A TX Data bus
UTOPIA port A TX Parity
UTOPIA port A RX clock
UTOPIA port A RX Start of Cell
1. UTOPIA port A RX Enable (in ATM)
2. UTOPIA port A RX Cell Available (in PHY)
CPU Bus Interface Pins
UTOPIA Interface Pins
Description (see notes 1-8)