MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 105

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

Address: 6080 (Hex)
Label: CMGCR
Reset Value: 0000 (Hex)
Address: 6082 (Hex)
Label: CMGSR
Reset Value: 0000 (Hex)
Note: Bits<6:0> will be set if the TESTS bit is set in the TDM Interface Control Register at 6000h.
OUT_SYNC_IE
LOSS_TIMRF
SRTST_UND
SRTST_OVR
SRTSR_UND
SRTSR_OVR
TIME_SERV
OUT_SYNC
TIM_ENA
Reserved
Reserved
REFFAIL
Label
Label
Position
Position
15:8
14:7
Bit
Bit
15
6
7
0
1
2
3
4
5
6
Table 59 - Clock Module General Control Register
Table 60 - Clock Module General Status Register
R/O/L
R/O/L
R/O/L
R/O/L
R/O/L
R/O/L
R/O/L
Type
Type
R/W
R/W
R/O
R/O
R/O
Out-Of-Sync Interrupt Enable - Timing Reference Cell Sub-Module. When enabled, a ‘1’ on
OUT_SYNC in Register 6082h will force a ‘1’ on TIM_SERV in Register 0002h.
Timing Enable - When ‘1’, enables the operation of the Timing Reference Cell Sub-Module
receive circuit for Adaptive Clock Recovery.
Will always read 00h.
Reference Clock Failure - Clock Generation Sub-Module. When ‘1’, indicates that the
REF8KCLK signal has failed. When this bit is ‘1’ and the FREERUN bits in the Master
Clock Generation Control Register (MCGCR at 6090h) are “01”, the external signal
FREERUN will be activated. MCLK should be at least 2048 times the REF8KCLK
frequency for proper operation. Writing a ‘1’ over this bit will clear it.
SRTS Transmit Underrun - SRTS Sub-Module. When ‘1’, indicates a slip underrun error
has occurred in the SRTS transmit circuit. This means that the TX_SAR (scheduler) is
sending RTSs faster than the SRTS Transmit Divider Register is generating them. Check
the scheduler vs. registers 60B0h, and 60B2h. Can be ignored when SRTS transmission is
not enabled. Writing a ‘1’ over this bit will clear it.
SRTS Transmit Overrun - SRTS Sub-Module. When ‘1’, indicates a slip overrun error has
occurred in the SRTS transmit circuit. This means that the SRTS Transmit Divider Register
is generating RTSs faster than the TX_SAR (scheduler) is sending them. Check the
scheduler vs. registers 60B0h, and 60B2h. Can be ignored when SRTS transmission is not
enabled. Writing a ‘1’ over this bit will clear it.
SRTS Receive Underrun - SRTS Sub-Module. When ‘1’, indicates a slip underrun error has
occurred in the SRTS receive circuit. This means that the RX_SAR is receiving RTSs faster
than the SRTS Transmit Divider Register is generating RTSs. Check registers 60B4h, and
60B6h. Can be ignored when SRTS reception is not enabled. Writing a ‘1’ over this bit will
clear it.
SRTS Receive Overrun - SRTS Sub-Module. When ‘1’, indicates a slip overrun error has
occurred in the SRTS receive circuit. This means that the SRTS Transmit Divider Register
is generating RTSs faster than the RX_SAR is receiving RTSs. Check registers 60B4h, and
60B6h. Can be ignored when SRTS reception is not enabled. Writing a ‘1’ over this bit will
clear it.
Loss of Timing Reference Cell stream - Timing Reference Cell Sub-Module. When ‘1’,
indicates a loss of timing reference cells (or marker) event has occurred (loss period
determined by Time-out field at 60A0h) while the Adaptive Clock Recovery state machine
was enabled (TIM_ENA bit set in Clock Module General Control Register at 6080h). Writing
a ‘1’ over this bit will clear it.
Out-Of-Sync - Timing Reference Cell Sub-Module. When ‘1’, indicates the Timing
Reference Cell state machine went out of sync. This bit is set only when the state
machine initially goes out of sync - if it stays out of sync., this bit will be cleared.
Writing a ‘1’ over this bit will clear it.
Will always read “000_0000_0”.
This bit is set if any of bits<6:0> are set.
Description
Description
MT90500
105