MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 81

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

5.1.2
The MT90500 uses a two-level interrupt structure, as shown in Figure 38. For each of five major modules
(TX_SAR, RX_SAR, UTOPIA, TDM Interface and TDM Clock) there is a Status register containing one or more
status bits, and a Control register containing corresponding mask bits (interrupt enable bits). There is also a
Main Status Register, and a Main Control Register.
For an interrupt to be asserted at the INT pin, the following three conditions must be met: a status bit in one of
the five module Status Registers must be asserted by an alarm event; the mask bit for that alarm event must be
set in that modules Control Register; and the mask bit for that module must be set in the Main Control Register.
Similarly, an interrupt event at the INT pin can be traced back to its source by reading the Main Status Register
to identify the module which is the source of the alarm, and then reading that module’s Status Register to
identify the particular alarm source. The interrupt can then be cleared by writing a ‘1’ over the status bit.
One for each major module
Status Register
Control Register
Status
Bits
Status
Mask
Bits
Interrupt Structure
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Figure 38. MT90500 Interrupt Structure
Main Status
Register
Main Control
Register
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MT90500
INT
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