MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 131

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

6.2.5
6.2.5.1
PTXCLK Period
PTXCLK Pulse Width (HIGH / LOW)
Input Setup Time - PTXCLAV VALID
to PTXCLK rising
Input Hold Time - PTXCLK rising to
PTXCLAV de-asserted
Output Delay - PTXCLK rising to
(PTXDATA[7:0] VALID and PTXEN and
PTXSOC asserted)
Output Hold Time - PTXCLK rising to
(PTXDATA[7:0] INVALID and PTXEN
and PTXSOC de-asserted)
Note 1: The MT90500 operates with the UTOPIA cell-level handshake.
Note 2: The MT90500 always inserts 1-4 idle cycles between cells on the TX UTOPIA port.
PTXCLK
PTXCLAV
PTXEN
PTXSOC
PTXDATA[7:0]
Characteristic
UTOPIA Interfaces
Primary UTOPIA Interface
t
PTXD
t
PTXIS
t
PTXP
X
Table 92 - Primary UTOPIA Interface Parameters - Transmit
Figure 57 - Primary UTOPIA Bus - Transmit Timing
H1
t
t
t
PTXH/L
t
t
t
Sym
PTXIS
PTXIH
PTXD
PTXH
PTXP
H2
t
PTXH
Min
16
10
H3
1
1
t
PTXIH
Typ
40
20
P45
4 cycles before the next cell
at least
Max
24
20
P46
t
PTXL
t
PTXH
Units
ns
ns
ns
ns
ns
ns
P47
PTXCLK = 25 MHz
C
C
L
L
= 50 pF
= 50 pF
P48
Test Conditions
t
t
PTXH
PTXH
MT90500
X
V
V
V
V
V
TT
TT
TT
TT
TT
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