MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 29

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

The MT90500 supports the following TDM timing modes:
•
In this mode, the MT90500 is configured as a TDM Timing Slave and all internal TDM timing is synchronized to
the TDM clock inputs: CLKx2, CLKx1, and FSYNC. The following sub-modes are also selectable:
TDM Timing Bus Slave - CLKx2 Reference (CLKMASTER = ‘0’ in TDM Bus Type Register at 6010h)
MCLK
CLKx2
SEC8K
CLKx1
FSYNC
MT90500
Square
SEC8K_SQ
•
•
•
External CPU Bus
SEC8KEN
The CLKx2 signal can be selected as single-ended or differential. (Differential CLKx2 allows com-
patibility with the H-MVIP bus.) In TDM Timing Slave, the CLKx2 signal can be input on the CLKx2
pin, or the differential CLKx2PI and CLKx2NI pins. This selection is made with CLKTYPE in the
TDM Bus Type Register at address 6010h. In TDM Timing Master, the CLKx2 signal is output on
the CLKx2/CLKx2PO pin, and an inverted clock is available on the CLKx2NO pin.
The CLKx1 can be an input at the CLKx1 pin, or it can be derived internally from CLKx2. This is
controlled by TCLKSYN (address 6010h). If the CLKx1 pin is not used as an input in TDM Slave
mode, it remains high-impedance.
TDM Timing Slave operation takes its 8 kHz framing from the FSYNC input pin, which would usu-
ally be driven by the TDM bus. To support other implementations, the REF8KCLK output remains
active in TDM Slave mode. An 8 kHz reference output can be made available at REF8KCLK,
selectable from the EX_8KA input, the SEC8K pin, or one of the internal dividers. In addition, the
FREERUN output can be used to monitor the presence of REF8KCLK.
1
0
ATM Cells
Master/Slave
1
0
Figure 3 - TDM Clock Selection and Generation Logic
SEC8KSEL
FS_INT
FSYNC
FS_INT
EX_8KA_INT
FNXI
SRTS Clock
Recovery
Recovery
Adaptive
Clock
SRTS
Bus Timing
Generation
Main TDM
Clock
Logic
and
Square
1 0
DIVCLK_SRC
1
0
All control bits shown are in Master Clock Generation Control Register (6090h).
(16.384 MHz)
DIV1...8
EX_8KA
CLK16
Divide by 2
RXVCLK
SEC8K_INT
EX_8KA_INT
PHLEN
to 16384
EX_8KA_SQ
1,2,4,or 8
Divide by
REFSEL<1:0>
BEPLL
CLKx2
CLKx1
FSYNC
0
2
1
3
Local TDM
Generation
1
0
Clock
Logic
Bus
Clock Absent
REF8KCLK
Detection
Detection
Logic
Logic
REF8KCLK
FREERUN
LOCx2
LOCx1
LSYNC
PLLCLK
(Optional)
External
MT90500
PLL
MT9041 or
other PLL
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