MT8941BP1 Zarlink Semiconductor, Inc., MT8941BP1 Datasheet
MT8941BP1
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MT8941BP1 Summary of contents
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... Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. Advanced T1/CEPT Digital Trunk PLL MT8941BE MT8941BP MT8941BPR MT8941BP1 MT8941BPR1 28 Pin PLCC* Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1 ...
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ENVC 2 23 MS0 22 C12i 3 21 MS1 F0i 19 F0b 6 18 MS2 7 17 C16i 8 16 ENC4o 9 15 C8Kb 10 C4o 14 11 VSS PIN PDIP Pin ...
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Pin Description (continued) Pin # Name DIP PLCC 11 13 C4o Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin 13 (C4b) at 4.096 MHz and has a rising edge in the ...
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Functional Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals to the interface circuits for T1 and CEPT (30+2) Primary Multiplex Digital Transmission links. As shown in the functional block diagram (see Figure 1), ...
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Input-to-Output Phase Relationship The no-correction window size is 324 ns for DPLL #1 and 32 µs for DPLL # possible for the relative phase of the reference signal to swing inside the no-correction window depending on its jitter ...
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MT8941B M M Mode Operation NORMAL Provides the T1 (1.544 MHz) clock synchronized to the falling edge of the input frame pulse (F0i DIVIDE-1 DPLL #1 divides the CVb input by ...
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Provides CEPT/ST-BUS 4.096 MHz and 2.048 MHz clocks and 8kHz frame pulse depending on the major mode selected Provides CEPT/ST-BUS 4.096 MHz & 2.048 MHz clocks depending on the major ...
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Mode NORMAL MODE: Provides the T1 (1.544 MHz) clock synchronized to the falling edge of the input frame pulse (F0i ...
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When MS2 is HIGH, the F0b pin provides the frame pulse output compatible with the ST-BUS format and locked to the internal or external input signal as determined by the other mode select pins. Table 4 summarizes the modes of ...
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The T1 and CEPT standards specify that, for free running equipment, the output clock tolerance must be less than or equal to ±32ppm and ±50ppm respectively. This requirement restricts the oscillators of DPLL #1 and DPLL #2 to have maximum ...
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Figure 6 - The Jitter Transfer Function for PLL1 Figure 7 - The Jitter Transfer Function for PLL2 However, if DPLL #1 and DPLL #2 are daisy-chained as shown in Figures 9 and 10, the output clock tolerance of DPLL ...
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Differences between MT8941B and MT8940 The MT8941B and MT8940 are pin and mode compatible for most applications. However, the user should take note of the following differences between the two parts. a) Distributed Timing 8 kHz Reference Signal M U ...
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Besides the improved jitter performance, the MT8941B differs from the MT8940 in five other areas: 1. Input pins on the MT8941B do not incorporate internal pull-up or pull-down resistors. In addition, the output con- figuration of the bidirectional C8Kb pin ...
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Crystal Clock MT8941B (12.352 MHz) MS0 MS1 MS2 MS3 F0i C12i EN CV C8Kb C16i EN C4o EN C2o Crystal Clock (16.384 MHz Figure 9 - Synchronization at the Master End of the T1 Transmission Link Crystal ...
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MS0 MS1 MS2 MS3 F0i C12i EN CV C8Kb Crystal Clock C16i (16.384 MHz) EN C4o EN C2o V SS Figure 11 - Synchronization at the Master End of the CEPT Digital Transmission Link At the slave end of the ...
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MS0 MS1 MS2 MS3 F0i C12i EN C8Kb Crystal Clock C16i (16.384 MHz Figure 12 - Synchronization at the Slave End of the CEPT Digital Transmission Link Figures 11 and 12 show how the MT8941B can ...
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MT8941B MS0 MS1 MS2 MS3 F0i C12i EN CV C8Kb Crystal Clock C16i (16.384 MHz) EN C4o EN C2o RST SS C Figure 13 - Generation of the ST-BUS Timing Signals Absolute Maximum Ratings* - Voltages are ...
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DC Electrical Characteristics - Voltages are with respect to ground (V ± ° V =5.0V 5%; V =0V Characteristics 1 S Supply Current Input HIGH voltage (For all ...
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AC Electrical Characteristics - Voltages are with respect to ground (V Characteristics 1 CVb output (1.544 MHz) rise time 2 CVb output (1.544 MHz) fall time D 3 CVb output (1.544 MHz) clock P period CVb ...
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V OH F0b FPL t W4oH V OH C4b W4oL V OH C4o 42LH t 42HL V OH C2o W2oL V OH C2o V OL Figure 16 - ...
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AC Electrical Characteristics Characteristics 1 C4b output clock period 2 C4b output clock width (HIGH) 3 C4b output clock width (LOW) 4 C4b output clock rise time 5 C4b clock output fall ...
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Voltages are with respect to ground (V AC Electrical Characteristics Characteristics 1 Master clocks input rise time 2 Master clocks input fall time 3 Master clock period (12.352 MHz Master clock period K ...
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Figure 18 - External Inputs on C4b and F0b for the DPLL #2 † - Voltages are with respect to ground (V AC Electrical Characteristics Characteristics 1 Delay from Enable to Output (HIGH to THREE STATE Delay from ...
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AC Electrical Characteristics - Uncommitted NAND Gate Voltages are with respect to ground (V ) unless otherwise stated. SS Characteristics 1 Propagation delay (LOW to HIGH), input output 2 Propagation delay (HIGH to LOW), input ...
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