MT8941BP1 Zarlink Semiconductor, Inc., MT8941BP1 Datasheet - Page 15

• Manufacturer Part Number: MT8941BP1
• Manufacturer: Zarlink Semiconductor, Inc.

At the slave end of the link (Figure 10) both the DPLLs are in NORMAL mode, with DPLL #2 providing the ST-BUS
timing signals locked to the 8 kHz frame pulse (E8Ko) extracted from the received signal on the T1 line. The
regenerated frame pulse is looped back to DPLL #1 to provide the T1 line clock, which is the same as the master
end.
The 12.352 MHz and 16.384 MHz crystal clock sources are necessary for DPLL #1 and #2, respectively.
Synchronization and Timing Signals for the CEPT Transmission Link
The MT8941B can be used to provide the timing and synchronization signals for the MH89790/790B, Zarlink’s
CEPT (30+2) Digital Trunk Interface Hybrid. Since the operational frequencies of the ST-BUS and the CEPT
primary multiplex digital trunk are the same, only DPLL #2 is required.
Crystal Clock
(16.384 MHz)
Figure 11 - Synchronization at the Master End of the CEPT Digital Transmission Link
MS0
MS1
MS2
MS3
F0i
C12i
EN
C8Kb
C16i
EN
EN
V
SS
CV
C4o
C2o
C
MT8941B
RST
V
C4b
C2o
F0b
DD
Y
R
o
Zarlink Semiconductor Inc.
MT8941B
V
DD
15
DPLL #1 - NOT USED
DPLL #2 - FREE-RUN
C2i
F0i
MH89790B
Mode of Operation for the MT8941B
OUTA
OUTB
DSTo
CSTo
CSTi0
CSTi1
DSTi
RxR
RxT
TRANSMIT
RECEIVE
(MS0=1; MS1=0; MS2=1; MS3=1)
MULTIPLEX
MT8980/81
PRIMARY
SWITCH
ST-BUS
DIGITAL
CEPT
LINK
Data Sheet