ST8024T Sitronix Technology, ST8024T Datasheet - Page 7

• Manufacturer Part Number: ST8024T
• Description: COM/SEG LCD Driver
• Manufacturer: Sitronix Technology

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7.
7.1
(Segment mode)
Preliminary Ver 0.12
/DISPOFF
ElO
SYMBOL
V
V
V
DI
LGND
12L
43L
GND
XCK
0L
S/C
V
V
L/R
MD
FR
1
LP
7
, V
, V
, V
, EIO
-DI
DD
SS
FUNCTIONAL DESCRIPTION
Pin Functions
0R
12R
43R
0
2
Logic system power supply pin,
Ground pin
Logic ground pin
Connect to GND by ITO on LCD panel.
Bias power supply pins for LCD drive voltage
Input pins for display data
Clock input pin for taking display data
Latch pulse input pin for display data
Input pin for selecting the reading direction of display data
Control input pin for output of non-select level
AC signal input pin for LCD drive waveform
Mode selection pin
Segment mode/common mode selection pin
Input/output pins for chip selection
Connected to +2.5 to +5.5 V.
Do not short LGND with GND and Vss by ITO on LCD panel
Connect it to GND on PCB or FPC.
Normally use the bias voltages set by a resistor divider
Ensure that voltages are set such that V
V
voltage which is assigned by specification for each power pin
In 4-bit parallel mode, DI
connected to LGND or V
In 8-bit parallel mode, All DI
Refer to section 7.2.2.
Data is read at the falling edge of the clock pulse.
Data is latched at the falling edge of the clock pulse.
When set to LGND level "L", data is read sequentially from Y
When set to V
Refer to section 7.2.2.
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
When set to LGND level "L", the LCD drive output pins (Y
When set to "L", the contents of the line latch are reset, but the display data are read in
the
data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is
canceled, the driver outputs non-select level (V
the data latch at the next falling edge of the LP. At that time, if /DISPOFF removal time
does not correspond to what is shown in AC characteristics, it can not output the
reading data correctly.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the line latch output
signal and the FR signal.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
When set to LGND level "L", 8-bit parallel input mode is set.
When set to V
Refer to section 7.2.2.
When set to V
When L/R input is at LGND level "L", ElO
When L/R input is at V
controls the LCD drive circuit.
iL
and V
iR
(i = 0,12, 43) must connect to an external power supply, and supply regular
DD
DD
DD
level "H", data is read sequentially from Y
level "H", 4-bit parallel input mode is set.
level "H", segment mode is set.
DD
3
DD
level "H", ElO
-DI
.
7
0
-Dl
are the display data input pins, and DI
Page 7/26
0
pins are the display data input pins.
FUNCTION
1
is set for input, and EIO
SS
1
is set for output, and EIO
< V
43
12
< V
or V
12
43
< V
), then outputs the contents of
0
1
.
1
-Y
to Y
240
240
) are set to level Vss.
to Y
240
2
is set for output.
.
1
2
7
.
is set for input.
-DI
4
must be
ST8024T
2008/01/24