ST8024T Sitronix Technology, ST8024T Datasheet - Page 8

• Manufacturer Part Number: ST8024T
• Description: COM/SEG LCD Driver
• Manufacturer: Sitronix Technology

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(Common mode)
Preliminary Ver 0.12
/DISPOFF
SYMBOL
V
V
V
Y
LGND
12L
43L
GND
EIO
1
0L
ElO
V
V
L/R
MD
FR
LP
-Y
, V
, V
, V
DD
SS
240
1
2
0R
12R
43R
LCD drive output pins
Logic system power supply pin, connected to +2.5 to +5.5 V.
Ground pin
Logic ground pin
Connect to GND by ITO on LCD panel.
Bias power supply pins for LCD drive voltage
Shift data input/output pin for bi-directional shift register
Shift data input/output pin for bi-directional shift register
Shift clock pulse input pin for bi-directional shift register
Input pin for selecting the shift direction of bi-directional shift register
Control input pin for output of non-select level
AC signal input pin for LCD drive waveform
Mode selection pin
During output, set to "H" while LP • XCK is "H" and after 240 bits of data have been
read, set
"H".
During input, the chip is selected while El is set to "L" after the LP signal is input. The
chip is non-selected after 240 bits of data have been read.
Corresponding directly to each bit of the data latch, one level (V
selected and output.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Do not short LGND with GND and Vss by ITO on LCD panel
Connect it to GND on PCB or FPC.
Normally use the bias voltages set by a resistor divider.
Ensure that voltages are set such that V
V
voltage which is assigned by specification for each power pin.
Output pin when L/R is at LGND level "L', input pin when L/R is at V
When L/R = H, ElO
When L/R = L, ElO
Refer to section 7.2.2.
Input pin when L/R is at LGND level "L", output pin when L/R is at V
When L/R = L, EIO
When L/R = H, EIO
Refer to section 7.2.2.
Data is shifted at the falling edge of the clock pulse.
Data is shifted from Y
Y
Refer to section 7.2.2.
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
When set to LGND level "L", the LCD drive output pins (Y
When set to "L”, the contents of the shift register are reset to not reading data. When
the /DISPOFF function is canceled, the driver outputs non-select level (V
the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF
removal time does not correspond to what is shown in AC characteristics, the shift data
is not read correctly.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the shift register
output signal and the FR signal.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
When set to LGND level "L", single mode operation is selected; when set to V
to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to
iL
240
and V
when set to V
iR
(i = 0,12, 43) must connect to an external power supply, and supply regular
DD
1
2
1
2
is used as output pin, it won't be pulled down.
is used as input pin, it will be pulled down.
is used as input pin, it will be pulled down.
level "H".
is used as output pin, it won't be pulled down.
240
to Y
1
when set to LGND level "L", and data is shifted from Y
Page 8/26
FUNCTION
SS
< V
43
< V
12
< V
0
1
.
-Y
240
) are set to level LGND.
0
, V
12
DD
DD
, V
level "H".
level "H".
43
12
, or V
or V
DD
ST8024T
SS
43
level
) is
), and
2008/01/24
1
to