CA3318 Intersil Corporation, CA3318 Datasheet
CA3318
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CA3318 Summary of contents
Page 1
... The overflow bit makes possible the connection of two or more CA3318s in series to increase the resolution of the conversion system. A series connection of two CA3318s may be used to produce a 9-bit high speed converter. Operation of two CA3318s in parallel doubles the conversion speed (i.e., increases the sampling rate from 15MHz to 30MHz) ...
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... REF (NOTE 1) 15 COMPARATOR # 50K CLOCK 18 PHASE ANALOG 17 GND NOTE: 1. Cascaded Auto Balance (CAB). CA3318 COUNT CAB # 256 LATCH LATCH 256 256 COUNT CAB # 193 LATCH LATCH COUNT CAB ...
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... 5V 6.4V REF REF TEST CONDITIONS LSB IN REF LSB IN REF 2 (Note 1) CA3318 CLK = Square Wave f = 15MHz 100kHz 15MHz 4MHz 15MHz 100kHz 15MHz 4MHz 15MHz 100kHz 15MHz 4MHz S IN ...
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... The clock input is a CMOS inverter with a 50k feedback resistor and may be AC coupled with 1V 4. Parameter not tested, but guaranteed by design or characterization. Timing Waveforms COMPARATOR DATA IS LATCHED CLOCK (PIN 18) IF PHASE (PIN 19 LOW CLOCK IF SAMPLE PHASE IS HIGH N CA3318 5V 6.4V REF REF TEST CONDITIONS Note 4 Note 4 ...
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... BALANCE CLOCK NO MAX LIMIT DATA FIGURE 3A. STANDBY IN INDEFINITE AUTO BALANCE (SHOWN WITH PHASE = LOW) SAMPLE CLOCK N 500ns MAX DATA FIGURE 3B. STANDBY IN SAMPLE (SHOWN WITH PHASE = LOW) CA3318 DIS DATA HIGH IMPEDANCE IMPEDANCE DATA IMPEDANCE FIGURE 2. OUTPUT ENABLE TIMING DIAGRAM AUTO ...
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... FIGURE 4. DEVICE CURRENT vs SAMPLE FREQUENCY 8 15MHz 1MHz S I 7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 -40 -30 -20 - TEMPERATURE ( FIGURE 6. ENOB vs TEMPERATURE 1.20 1.08 0.96 0.84 0.72 0.60 0.48 0.36 0.24 0. (MHz) S FIGURE 8. NON-LINEARITY vs SAMPLE FREQUENCY CA3318 -50 FIGURE 5. DEVICE CURRENT vs TEMPERATURE 1. 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0. FIGURE 7. NON-LINEARITY vs TEMPERATURE 1. 1.80 1.60 1.40 INL 1.20 1.00 0.80 0.60 DNL 0 ...
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... True Don’t Care Theory of Operation A sequential parallel technique is used by the CA3318 converter to obtain its high speed operation. The sequence consists of the “Auto-Balance” phase, 1, and the “Sample Unknown” phase, 2. (Refer to the circuit diagram.) Each 1 conversion takes one clock cycle (see Note). With the phase ...
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... CA3318 Pulse-Mode Operation The CA3318 needs two of the same polarity clock edges to complete a conversion cycle: If, for instance, a negative going clock edge ends sample “N”, then data “N” will appear after the next negative going edge. Because of this require- ...
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... To obtain 9-bit resolution, two CA3318s can be wired together. Necessary ingredients include an open-ended ladder net- work, an overflow indicator, three-state outputs, and chip- enable controls - all of which are available on the CA3318. CA3318 The first step for connecting a 9-bit circuit is to totem-pole the ladder networks, as illustrated in Figure 13. Since the absolute resistance value of each ladder may vary, external trim of the mid-reference voltage may be required ...
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... CORR where 0.5dB. CORR +6.4V REF VIN1 0V TO 6.4V MID-POINT 6.4V REF DRIVER A FIGURE 13. USING TWO CA3318s FOR 9-BIT RESOLUTION CA3318 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal REF V + ...
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... F/10V TANTALUM A +4V TO +6.5V REFERENCE OPTIONAL CAP (SEE TEXT) 0.01 F CLOCK SOURCE INPUT SIGNAL AMPLIFIER/BUFFER (SEE TEXT) FIGURE 14. TYPICAL CIRCUIT CONFIGURATION FOR THE CA3318 WITH NO LINEARITY ADJUST AMP SIGNAL SOURCE SIGNAL GROUND - + ANALOG SUPPLIES FIGURE 15. TYPICAL SYSTEM GROUNDING/BYPASSING 75 1V P-P VIDEO INPUT 75 5pF NOTE: Ground-planing and tight layout are extremely important ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com CA3318 TABLE 1. OUTPUT CODE TABLE BINARY OUTPUT CODE ...