CS493002-CL Cirrus Logic, CS493002-CL Datasheet - Page 44

• Manufacturer Part Number: CS493002-CL
• Description: Multi-Standard Audio Decoder Family
• Manufacturer: Cirrus Logic

6.2.1.1.Writing a Byte in Intel Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Intel Parallel Host Mode Write Cycle are met.
The flow diagram shown in
the sequence of events that define a one-byte write
in Intel mode. The protocol presented in
will now be described in detail.
1) The host must first drive the A1 and A0 register
2) The host then indicates that the selected register
3) The host drives the data byte to the DATA[7:0]
4) Once the setup time for the write has been met,
44
Figure 24. Intel Mode, One-Byte Write Flow Diagram
address pins of the CS493XX with the address
of the desired Parallel I/O Register.
Host Message:
Host Control:
PCMDATA:
CMPDATA:
will be written. The host initiates a write cycle
by driving the CS and WR pins low.
pins of the CS493XX.
ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY
WRITE BYTE TO
WR (HIGH)
DATA [7:0]
CS (HIGH)
W R (LO W )
C S (LO W )
A[1:0]==00b.
A[1:0]==01b.
A[1:0]==10b.
A[1:0]==11b.
Figure 24
illustrates
Figure 24
6.2.1.2.Reading a Byte in Intel Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Intel Parallel Host Mode Read Cycle are met.
The flow diagram shown in
the sequence of events that define a one-byte read
in Intel mode. The protocol presented in
will now be described in detail.
1) The host must first drive the A1 and A0 register
2) The host now indicates that the selected register
3) Once the data is valid, the host can read the
Figure 25. Intel Mode, One-Byte Read Flow Diagram
the host ends the write cycle by driving the CS
and WR pins high.
address pins of the CS493XX with the address
of the desired Parallel I/O Register. Note that
only the Host Message register and the Host
Control register can be read.
Host Message:
Host Control:
will be read. The host initiates a read cycle by
driving the CS and RD pins low.
value of the selected register from the
DATA[7:0] pins of the CS493XX.
ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY
READ BYTE FROM
CS49300 Family DSP
RD (HIGH)
DATA [7:0]
CS (HIGH)
C S (LO W )
R D (LO W )
A[1:0]==00b.
A[1:0]==01b.
Figure 25
DS339PP4
illustrates
Figure 25