CS493002-CL Cirrus Logic, CS493002-CL Datasheet - Page 52

• Manufacturer Part Number: CS493002-CL
• Description: Multi-Standard Audio Decoder Family
• Manufacturer: Cirrus Logic

8.
In this section the process of booting and
downloading to the CS493XX will be covered as
well as how to perform a soft reset. Host boot and
autoboot and reset are covered in this section.
8.1. Host Boot
A flow diagram of a typical serial download
sequence and a typical parallel download sequence
will be presented, as well as pseudocode
representing a download sequence from the
programmers perspective. The pseudocode is
written in a general sense where function calls are
made to Write_* and Read_*. The * can be
replaced by I
sequence, and INTEL or MOTO for the parallel
download sequence, depending on the mode of host
communication. For each case the general
download algorithm is the same.
The download and boot procedure is accomplished
with RESET (pin 36), and the communication pins
discussed in
flow diagrams in
and Download Procedure,
Parallel Boot and Download Procedure, illustrate
typical boot and download procedures. When
reading in serial mode, you must check that
INTREQ is low to start reading. Similarly, in
parallel mode you must check HOUTRDY.
Table 9
Table 10
monic and actual hex value. These messages will
be used in the boot sequence.
Hardware configuration messages are used to
define the behavior of the DSP’s audio ports. A
more detailed description of the different hardware
configurations can be found in the
“Hardware Configuration” on page
The software configuration messages are specific
to each application. The application code user’s
guide for each application provides a list of all
52
BOOT PROCEDURE & RESET
defines the boot write messages and
defines the boot read messages in mne-
Section 6, “Control” on page
2
C or SPI for the serial download
Figure 33. Typical Serial Boot
and Figure 34. Typical
72.
Section 11,
32. The
pertinent configuration messages. Writing the
KICKSTART message to the CS493XX begins the
audio decode process. The KICKSTART message
will also be described in the user’s guide for each
application. Until the KICKSTART has been sent,
the decoder is in a wait state.
8.1.1. Serial Download Sequence
The following is a detailed description of a serial
download sequence for the CS493XX.
1) A download sequence is started when the host
2) The host should then send the boot message
3) If the initialization was successful the
issues a hard reset and holds the mode pins
appropriately (WR, RD, and PSEL).
DOWNLOAD_BOOT
causes the CS493XX to initialize itself for
download.
BOOT_SUCCESS_RECEIVED
Note: When reading from the chip in a serial
communication mode, the host must wait for the
interrupt request (INTREQ) to fall before
starting the read cycle.
APPLICATION_FAILURE
DOWNLOAD_BOOT
BAD_CHECKSUM
BOOT_SUCCESS
BOOT_ERROR
BOOT_ERROR
Table 10. Boot Read Messages
SOFT_RESET
INVALID_MSG
Table 9. Boot Write Messages
BOOT_START
INIT_FAILURE
INIT_FAILURE
MNEMONIC
RESERVED
RESERVED
MNEMONIC
CS49300 Family DSP
(0x000004).
0x000005
0x000001
0x000002
0x000003
0x000004
DS339PP4
VALUE
VALUE
0xFB
0xFC
0xFD
0xFE
0xF0
0xFA
0xFF
0x01
0x02
This