CS493002-CL Cirrus Logic, CS493002-CL Datasheet - Page 7
CS493002-CL
Manufacturer Part Number
CS493002-CL
Description
Multi-Standard Audio Decoder Family
Manufacturer
Cirrus Logic
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1.5. Switching Characteristics — RESET
(T
Notes: 1. The minimum RESET pulse listed above is valid only when using the recommended pull-up/pull-down
1.6. Switching Characteristics — CLKIN
(T
DS339PP4
RESET minimum pulse width low (-CL)
RESET minimum pulse width low (-IL)
All bidirectional pins high-Z after RESET low
Configuration bits setup before RESET high
Configuration bits hold after RESET high
CLKIN period for internal DSP clock mode
CLKIN high time for internal DSP clock mode
CLKIN low time for internal DSP clock mode
A
A
= 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
= 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
2. This specification is characterized but not production tested.
resistors on the RD, WR, PSEL and ABOOT mode pins. For Rev. D and older parts, pull-up/pull-down
resistors may be 4.7 k or 3.3 k. For Rev. E and newer parts, pull-up/pull-down resistors must be 3.3 k.
C L K IN
Parameter
Parameter
A ll B idirectional
Figure 2. CLKIN with CLKSEL = VSS = PLL Enable
P S E L, A B O O T
R D , W R ,
R E S E T
T
P ins
clkih
Figure 1. RESET Timing
T
clki
(Note 1)
(Note 1)
(Note 2)
T
T
rst2z
rstl
T
clkil
Symbol
Symbol
T
T
T
T
T
T
T
T
rsthld
rst2z
rstsu
clkih
T
clkil
clki
rstl
rstl
rstsu
T
rsthld
CS49300 Family DSP
L
L
Min
100
530
Min
50
15
35
18
18
= 20 pF)
= 20 pF)
-
3800
Max
Max
50
-
-
-
-
Unit
Unit
µs
µs
ns
ns
ns
ns
ns
ns
7
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