CS8406-IS Cirrus Logic, CS8406-IS Datasheet - Page 9
CS8406-IS
Manufacturer Part Number
CS8406-IS
Description
192 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
Manufacturer
Cirrus Logic
Datasheet
1.CS8406-IS.pdf
(43 pages)
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
Notes: 9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is
DS580F1
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
10. T
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For f
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate.
sch
sck
must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns.
CDOUT
< 1 MHz.
CDIN
CCLK
CS
Parameter
t css
t r2
L
= 20 pF)
Figure 3. SPI Mode timing
t dsu
t scl
t f2
(Note 10)
(Note 12)
(Note 12)
(Note 11)
(Note 9)
t sch
t dh
Symbol
t pd
t
f
t
t
t
t
t
t
csh
sch
dsu
t
t
t
sck
css
t
scl
dh
pd
r1
f1
r2
f2
MAX ((1/256 F
Min
1.0
20
66
40
15
0
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
t csh
S
+ 8), 66)
Max
100
100
6.0
50
25
25
-
-
-
-
-
CS8406
Units
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
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