ST5090 ST Microelectronics, ST5090 Datasheet - Page 6

• Manufacturer Part Number: ST5090
• Description: LOW VOLTAGE 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
• Manufacturer: ST Microelectronics

ST5090
be set by writing to bits 4 to 7 in register CR6. At-
tenuations in the range 0 to -30 dB relative to the
maximum level in 2 dB step can be programmed.
The input of this programmable amplifier is the
sum of several signals which can be selected by
writing to register CR4.:
V
power level up to 66mW into differentially con-
nected load impedance of 30 . Piezoceramic re-
ceivers up to 50nF can also be driven.
Differential outputs V
rectly drive an extra output. Preceding the outputs
is a programmable attenuation amplifier, which
must be set by writing to bits 0 to 3 in register
CR6. Attenuations in the range 0 to -30 dB rela-
tive to the maximum level in 2.0 dB step can be
programmed. The input of this programmable am-
plifier can be the sum of signals which can be se-
lected by writing to register CR4:
V
power level up to 66mW into differentially con-
nected load impedance of 30 . Piezoceramic re-
ceivers up to 50nF can also be driven.
BUZZER OUTPUT:
Single ended output BZ is intended to drive a
buzzer, via an external BJT, with a squarewave
pulse width modulated (PWM) signal the fre-
quency of which is stored into register CR8.
For some applications it is also possible to ampli-
tude modulate this PWM signal with a square-
wave signal having a frequency stored in register
CR9.
Maximum load for BZ is 5k and 50pF.
I
F
frame. It may have any duration from a single cy-
cle of MCLK to a squarewave. Three different re-
lationships may be established between the
Frame Sync input and the first time slot of frame
by setting bits DM1 and DM0 in register CR1.
6/29
.6 Digital Interface (Fig. 1)
FR+
Lr+
S
- Receive speech signal which has been de-
- Internally generated tone signal, (Tone ampli-
- Sidetone signal, the amplitude of which is pro-
- Receive speech signal which has been de-
- Internally generated tone signal, (Tone ampli-
- Sidetone signal, the amplitude of which is pro-
Frame Sync input determines the beginning of
coded and filtered,
tude is programmed with bits 4 to 7 of register
CR7),
grammed with bits 0 to 3 of register CR5
coded and filtered,
tude is programmed with bits 4 to 7 of register
CR7),
grammed with bits 0 to 3 of register CR5.
and V
and V
Lr-
FR-
outputs are capable of driving output
outputs are capable of driving output
Lr+
,V
Lr-
are intended to di-
Non delayed data mode is similar to long frame
timing on ST5080A: first time slot begins nomi-
nally coincident with the rising edge of F
native is to use delayed data mode, which is simi-
lar to short frame sync timing on ST5080A, in
which F
of MCLK earlier the frame beginning. In the case
of companded code only (bit CM = 1 in register
CRO) a time slot assignment circuit on chip may
be used with all timing modes, allowing connec-
tion to one of the two B1 and B2 voice data chan-
nels.
Two data formats are available: in Format 1, time
slot B1 corresponds to the 8 MCLK cycles follow-
ing immediately the rising edge of FS, while time
slot B2 corresponds to the 8 MCLK cycles follow-
ing immediately time slot B1.
In Format 2, time slot B1 is identical to Format 1.
Time slot B2 appears two bit slots after time slot
B1. This two bits space is left available for inser-
tion of the D channel data.
Data format is selected by bit FF (2) in register
CR0. Time slot B1 or B2 is selected by bit TS (1)
in Control Register CR1.
Bit EN (2) in control register CR1 enables or dis-
ables the voice data transfer on D
appropriate. During the assigned time slot, D
output shifts data out from the voice data register
on the rising edges of MCLK in the case of de-
layed and non-delayed normal modes or on the
falling edges of MCLK in the case of non-delayed
reverse mode. Serial voice data is shifted into D
input during the same time slot on the falling
edges of MCLK in the case of delayed and non-
delayed normal modes or on the rising edges of
MCLK in the case of non-delayed reverse mode.
D
when in the non selected time slots.
I
Control information or data is written into or read-
back from ST5090 via the serial control port con-
sisting of control clock CCLK, serial data input CI
and output CO, and Chip Select input, CS-. All
control instructions require 2 bytes as listed in Ta-
ble 1, with the exception of a single byte power-
up/down command.
To shift control data into ST5090, CCLK must be
pulsed high 8 times while CS- is low. Data on CI
input is shifted into the serial input register on the
rising edge of each CCLK pulse. After all data is
shifted in, the content of the input shift register is
decoded, and may indicate that a 2nd byte of
control data will follow. This second byte may
either be defined by a second byte-wide CS-
pulse or may follow the first contiguously, i.e. it is
not mandatory for CS- to return high in between
the first and second control bytes. At the end of
the 2nd control byte, data is loaded into the ap-
.7 Control Interface:
X
is in the high impedance Tristate condition
S
input must be high at least a half cycle
X
and D
S
. Alter-
R
as
X
R