AD9639 Analog Devices, Inc., AD9639 Datasheet - Page 20

• Manufacturer Part Number: AD9639
• Description: Quad, 12-bit, 170 Msps/210 Msps Serial Output 1.8 V Adc
• Manufacturer: Analog Devices, Inc.

AD9639
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
due only to aperture jitter (t
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 48).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9639.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note, the AN-756 Application
Note, and the Analog Dialogue article, “Analog-to-Digital Converter
Clock Optimization: A Test Engineering Perspective” (Volume 42,
Number 2, February 2008) for in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
SNR Degradation = 20 × log 10(1/2 × π × f
130
120
110
100
90
80
70
60
50
40
30
1
10 BITS
RMS CLOCK JITTER REQUIREMENT
Figure 48. Ideal SNR vs. Input Frequency and Jitter
ANALOG INPUT FREQUENCY (MHz)
10
J
) can be calculated as follows:
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
100
A
× t
16 BITS
14 BITS
12 BITS
J
)
1000
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A
)
Power Dissipation
As shown in Figure 49 and Figure 50, the power dissipated by
the AD9639 is proportional to its clock rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and the bias current of the
digital output drivers.
Figure 49. Supply Current vs. Encode for f
Figure 50. Supply Current vs. Encode for f
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
50
50
70
70
90
90
110
POWER
I
ENCODE (MSPS)
ENCODE (MSPS)
DRVDD
I
AVDD
POWER
I
I
DRVDD
AVDD
110
130
150
IN
IN
= 84.3 MHz, f
= 84.3 MHz, f
130
170
150
190
SAMPLE
SAMPLE
= 170 MSPS
= 210 MSPS
170
210
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0