AD9639 Analog Devices, Inc., AD9639 Datasheet - Page 6

• Manufacturer Part Number: AD9639
• Description: Quad, 12-bit, 170 Msps/210 Msps Serial Output 1.8 V Adc
• Manufacturer: Analog Devices, Inc.

AD9639
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
otherwise noted.
Table 4.
Parameter
CLOCK
DATA OUTPUT PARAMETERS
TERMINATION CHARACTERISTICS
APERTURE
OUT-OF-RANGE RECOVERY TIME
1
2
3
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
Receiver dependent.
See the Serial Data Frame section.
Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Data Output Period or UI
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (t
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
Data Rate per Channel (NRZ)
Deterministic Jitter
Random Jitter
Channel-to-Channel Bit Skew
Channel-to-Channel Packet Skew
Output Rise/Fall Time
Differential Termination Resistance
Aperture Delay (t
Aperture Uncertainty (Jitter)
(DOUT + x, DOUT − x)
1
LOCK
A
)
)
EL
EH
)
)
2
MIN
3
= −40°C, T
25°C
Temp
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
MAX
= +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless
Min
100
2.65
2.65
Rev. 0 | Page 6 of 36
AD9639BCPZ-170
Typ
2.9
2.9
1/(20 × f
50
0.8
4
250
50
3.4
10
6
0
±1
50
100
1.2
0.2
1
CLK
)
Max
170
40
Min
100
2.15
2.15
AD9639BCPZ-210
Typ
2.4
2.4
1/(20 × f
50
0.8
4
250
50
4.2
10
0
±1
50
100
1.2
1
6
0.2
CLK
)
Max
210
40
Unit
MSPS
ns
ns
Seconds
%
UI
μs
ns
μs
CLK cycles
Gbps
ps
ps rms
Seconds
CLK cycles
ps
Ω
ns
ps rms
CLK cycles