AD9639 Analog Devices, Inc., AD9639 Datasheet - Page 27

• Manufacturer Part Number: AD9639
• Description: Quad, 12-bit, 170 Msps/210 Msps Serial Output 1.8 V Adc
• Manufacturer: Analog Devices, Inc.

Setting Bit 2 in the output mode register (Address 0x14) allows
the user to invert the digital outputs from their nominal state.
This is not to be confused with inverting the serial stream to an
LSB first mode. In default mode, as shown in Figure 2, the MSB
is first in the data output serial stream. However, this order can
be inverted so that the LSB is first in the data output serial stream.
There are eight digital output test pattern options available that
can be initiated through the SPI (see Table 12 for the output bit
sequencing options). This feature is useful when validating
receiver capture and timing. Some test patterns have two serial
sequential words and can be alternated in various ways, depending
on the test pattern selected. Note that some patterns do not
adhere to the data format select option. In addition, custom
user-defined test patterns can be assigned in the user pattern
registers (Address 0x19 through Address 0x20).
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 2
of the PN sequence short and how it is generated can be found
in Section 5.1 of the ITU-T O.150 (05/96) recommendation.
The only difference is that the starting value must be a specific
value instead of all 1s (see Table 11 for the initial values).
Table 12. Flexible Output Test Modes
Output Test Mode
Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1
All test mode options except PN sequence long and PN sequence short can support 8- to 14-bit word lengths to verify data capture to the receiver.
Pattern Name
Off (default)
Midscale short
+Full-scale short
−Full-scale short
Checkerboard
PN sequence long
PN sequence short
One-/zero-word toggle
9
− 1 (511) bits. A description
1
1
Digital Output Word 1
N/A
1000 0000 0000
1111 1111 1111
0000 0000 0000
1010 1010 1010
N/A
N/A
1111 1111 1111
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The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 2
description of the PN sequence long and how it is generated can
be found in Section 5.6 of the ITU-T O.150 (05/96) standard.
The only differences are that the starting value must be a specific
value instead of all 1s (see Table 11 for the initial values) and
that the AD9639 inverts the bit stream with relation to the ITU-T
standard.
Table 11. PN Sequence
Sequence
PN Sequence Short
PN Sequence Long
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
Digital Output Word 2
N/A
Same
Same
Same
0101 0101 0101
N/A
N/A
0000 0000 0000
Initial
Value
0x0DF
0x29B80A
23
First Three Output Samples
(MSB First)
0xDF9, 0x353, 0x301
0x591, 0xFD7, 0x0A3
− 1 (8,388,607) bits. A
Subject to Data
Format Select
Yes
Yes
Yes
Yes
No
Yes
Yes
No
AD9639