AD9639 Analog Devices, Inc., AD9639 Datasheet - Page 26

• Manufacturer Part Number: AD9639
• Description: Quad, 12-bit, 170 Msps/210 Msps Serial Output 1.8 V Adc
• Manufacturer: Analog Devices, Inc.

AD9639
Figure 59 shows an example of the digital output (default) data
eye and a time interval error (TIE) jitter histogram with trace
lengths less than 6 inches on standard FR-4 material. Figure 60
shows an example of trace lengths exceeding 12 inches on stan-
dard FR-4 material. Note that the TIE jitter histogram reflects
the decrease of the data eye opening as the edge deviates from
the ideal position. It is the user’s responsibility to determine
whether the waveforms meet the timing budget of the design
when the trace lengths exceed 6 inches.
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs to drive longer
trace lengths (see Address 0x15 in Table 15). Even though this
produces sharper rise and fall times on the data edges and is less
prone to bit errors, the power dissipation of the DRVDD supply
increases when this option is used. See the Memory Map section
for more details.
–200
–400
–600
–200
–400
–600
600
400
200
600
400
200
Figure 60. Digital Outputs Data Eye with Trace Lengths Greater Than 12 Inches on Standard FR-4, External 100 Ω Terminations at Receiver
0
0
Figure 59. Digital Outputs Data Eye with Trace Lengths Less Than 6 Inches on Standard FR-4, External 100 Ω Terminations at Receiver
(y1)
(y2)
(Δy)
EYE: ALL BITS
OFFSET: 0.015
ULS: 5000: 40044, TOTAL: 12000: 80091
–200
–200
(y1)
(y2)
(Δy)
EYE: ALL BITS
OFFSET: 0.015
ULS: 5000: 40044, TOTAL 8000: 40044
–375.023m
+409.847m
+784.671m
HEIGHT1: EYE DIAGRAM
HEIGHT1: EYE DIAGRAM
–402.016m
+398.373m
+800.389m
–100
–100
TIME (ps)
TIME (ps)
0
0
100
100
200
200
+
+
1
1
600
500
400
300
200
100
300
250
200
150
100
50
0
0
–30
–50
Rev. 0 | Page 26 of 36
TIE1: HISTOGRAM
TIE1: HISTOGRAM
–10
TIME (ps)
TIME (ps)
0
10
The format of the output data is offset binary by default.
Table 10 provides an example of this output coding format.
To change the output data format to twos complement or gray
code, see the Memory Map section (Address 0x14 in Table 15).
Table 10. Digital Output Coding
Code
4095
2048
2047
0
The lowest typical clock rate is 100 MSPS. For clock rates slower
than 100 MSPS, the user can set Bit 3 to 0 in the serial control
register (Address 0x21 in Table 15). This option allows the user
to adjust the PLL loop bandwidth to use clock rates as low as
50 MSPS.
30
50
(VIN + x) − (VIN − x),
Input Span = 1.25 V p-p (V)
+0.625
0.00
−0.000305
−0.625
2
+
+
2
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
–10
–12
–14
–10
–12
–14
–2
–4
–6
–8
–2
–4
–6
–8
–0.5
0
–0.5
0
TJ@BERI: BATHTUB
TJ@BERI: BATHTUB
ULS
ULS
0
0
Digital Output Offset
Binary ([D11:D0])
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
0.5
0.5
+
3
3
+