LTC2262-14 Linear Dimensions Semiconductor, LTC2262-14 Datasheet - Page 11

• Manufacturer Part Number: LTC2262-14
• Description: 150Msps Ultralow Power 1.8V ADC
• Manufacturer: Linear Dimensions Semiconductor

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PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
A
A
GND (Pin 3): ADC Power Ground.
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
PAR/SER (Pin 8): Programming Mode Selection Pin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to V
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or the V
logic signal.
PIN FUNCTIONS
TYPICAL PERFORMANCE CHARACTERISTICS
IN
IN
+
–
45
40
35
30
25
20
15
10
5
0
(Pin 1): Positive Differential Analog Input.
(Pin 2): Negative Differential Analog Input.
0
LTC2262-14: IO
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
1.75mA LVDS
3.5mA LVDS
SAMPLE RATE (Msps)
50
DD
VDD
1.8V CMOS
of the part and not be driven by a
vs Sample
100
1.2V CMOS
226214 G14
150
DD
to enable the
74
73
72
71
70
69
68
67
66
0.6
LTC2262-14: SNR vs SENSE,
f
IN
= 5MHz, –1dB
0.7
0.8
SENSE PIN (V)
0.9
V
to ground with 0.1μF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
ENC
rising edge.
ENC
starts on the falling edge.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = V
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = V
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
DD
1
+
–
(Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
1.1
(Pin 11): Encode Input. Conversion starts on the
(Pin 12): Encode Complement Input. Conversion
1.2
226214 G15
1.3
DD
), CS controls the clock duty cycle
73
72
71
70
69
0
LTC2262-14: SNR vs Sample Rate
and Digital Output Mode, 30MHz Sine
Wave Input, –1dB
25
LTC2262-14
SAMPLE RATE (Msps)
50
DD
), SCK controls the
DDR CMOS
75
100
125
11
CMOS
LVDS
226214 G18
226214p
150