LTC2262-14 Linear Dimensions Semiconductor, LTC2262-14 Datasheet - Page 21

• Manufacturer Part Number: LTC2262-14
• Description: 150Msps Ultralow Power 1.8V ADC
• Manufacturer: Linear Dimensions Semiconductor

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APPLICATIONS INFORMATION
mode requires at least 100 clock cycles. If the application
demands very accurate DC settling then an additional
50μs should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2262-14 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more fl exibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V
inputs that set certain operating modes. These pins can
be tied to V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = V
PIN
CS
SCK
SDI
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
DESCRIPTION
Clock Duty Cycle Stabilizer Control Bit
Digital Output Mode Control Bit
Power Down Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
0 = Full-Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
0 = Normal Operation
1 = Sleep Mode
DD
(3.5mA LVDS Current, Internal Termination Off)
DD
. The CS, SCK and SDI pins are binary logic
or ground, or driven by 1.8V, 2.5V or 3.3V
DD
)
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the fi rst 16 rising edges of
SCK. Any SCK rising edges after the fi rst 16 are ignored.
The data transfer ends when CS is taken high again.
The fi rst bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The fi nal eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
then SDO can be left fl oating and no pull-up resistor is
needed.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The fi rst serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
GROUNDING AND BYPASSING
The LTC2262-14 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with
an internal ground plane is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the V
capacitors must be located as close to the pins as possible.
DD
, OV
DD
, V
CM
, V
REF
, REFH and REFL pins. Bypass
LTC2262-14
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