LTC2262-14 Linear Dimensions Semiconductor, LTC2262-14 Datasheet - Page 22

• Manufacturer Part Number: LTC2262-14
• Description: 150Msps Ultralow Power 1.8V ADC
• Manufacturer: Linear Dimensions Semiconductor

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APPLICATIONS INFORMATION
LTC2262-14
Of particular importance is the 0.1μF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2μF capacitor
between REFH and REFL can be somewhat further away.
The V
as possible. To make space for this the capacitor on V
can be further away or on the back of the PC board. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
22
Table 3. Serial Programming Mode Register Map
REGISTER A0: RESET REGISTER (ADDRESS 00h)
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
Bit 7
Bits 6-0
Bits 7-2
Bits 1-0
Bits 7-4
Bit 3
Bits 2-1
Bit 0
RESET
CM
D7
D7
D7
X
X
capacitor should be located as close to the pin
RESET
0 = Not Used
1 = Software Reset. All Mode Control Registers are Reset to 00h. This Bit is Automatically Set Back to Zero After the Reset is Complete
Unused, Don’t Care Bits.
Unused, Don’t Care Bits.
PWROFF1:PWROFF0
00 = Normal Operation
01 = Nap Mode
10 = Not Used
11 = Sleep Mode
Unused, Don’t Care Bits.
CLKINV
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
CLKPHASE1:CLKPHASE0
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT
10 = CLKOUT
11 = CLKOUT
Note: If the CLKOUT Phase Delay Feature is Used, the Clock Duty Cycle Stabilizer Must Also be Turned On
DCS
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
D6
D6
D6
X
X
X
Clock Duty Cycle Stabilizer Bit
Output Clock Invert Bit
+
+
+
/CLKOUT
/CLKOUT
/CLKOUT
Software Reset Bit
–
–
–
Delayed by 45° (Clock Period • 1/8)
Delayed by 90° (Clock Period • 1/4)
Delayed by 135° (Clock Period • 3/8)
D5
D5
D5
X
X
Power Down Control Bits
X
Output Clock Phase Delay Bits
D4
D4
D4
X
X
X
REF
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fi ll and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2262-14 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board.
CLKINV
D3
D3
D3
X
X
CLKPHASE1
D2
D2
D2
X
X
CLKPHASE0
PWROFF1
D1
D1
D1
X
PWROFF0
DCS
D0
D0
D0
X
226214p