LTC3858-1 Linear Technology Corporation, LTC3858-1 Datasheet - Page 22

• Manufacturer Part Number: LTC3858-1
• Description: Dual 2-Phase Synchronous Step-Down Controller
• Manufacturer: Linear Technology Corporation

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LTC3858-1
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously
for as long as the overvoltage condition persists; if V
returns to a safe level, normal operation automatically
resumes.
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The LTC3858-1 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass fi lter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked to
the rising edge of an external clock signal applied to the
PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET
is thus 180 degrees out of phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
Rapid phase locking can be achieved by pre-biasing the
VCO’s input voltage to the desired PLL frequency before
the external clock is applied. This is achieved by con-
necting a resistor between the FREQ pin and ground.
The FREQ pin has an internal 20μA pull-up current that
develops a VCO input voltage. Choosing the appropriate
resistor can pre-bias the VCO input to the desired fre-
quency. Once the VCO input is pre-biased to the proper
frequency, the lowpass fi lter only needs to adjust slightly
to achieve phase lock. This is advantageous over other
types of PLLs that need to pass though a large range of
undesirable frequencies before synchronizing. Although
pre-biasing of the VCO input voltage is not required, it will
avoid sweeping the oscillator from 350kHz or 535kHz to
the fi nal PLL frequency.
Note that the LTC3858-1 can only be synchronized to an
external clock whose frequency is within range of the
LTC3858-1’s internal VCO, which is nominally 50kHz to
900kHz. This is guaranteed to be between 75kHz and
850kHz.
APPLICATIONS INFORMATION
22
OUT
When not prebiased, applying an external clock will invoke
traditional PLL operation. If the external clock frequency is
greater than the internal oscillator’s frequency, f
current is sourced continuously from the phase detector
output, pulling up the VCO input. When the external clock
frequency is less than f
pulling down the VCO input. If the external and internal
frequencies are the same but exhibit a phase difference,
the current sources turn on for an amount of time cor-
responding to the phase difference. The voltage at the
VCO input is adjusted until the phase and frequency of
the internal and external oscillators are identical. At the
stable operating point, the phase detector output is high
impedance and the internal fi lter capacitor, C
voltage at the VCO input.
Typically, the external clock (on the PLLIN/MODE pin)
input high threshold is 1.6V, while the input low threshold
is 1.1V.
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
Any of the Above
Figure 9. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
FREQ PIN
Resistor
INTV
0V
1000
900
800
700
200
100
600
500
400
300
CC
0
15
25
35 45 55
FREQ PIN RESISTOR (kΩ)
PLLIN/MODE PIN
OSC
External Clock
DC Voltage
DC Voltage
DC Voltage
65 75 85 95 105 115 125
, current is sunk continuously,
38581 F09
Phase–Locked to
50kHz–900kHz
External Clock
FREQUENCY
LP
350kHz
535kHz
, holds the
OSC
, then
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