LTC3858-1 Linear Technology Corporation, LTC3858-1 Datasheet - Page 24

• Manufacturer Part Number: LTC3858-1
• Description: Dual 2-Phase Synchronous Step-Down Controller
• Manufacturer: Linear Technology Corporation

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LTC3858-1
4. Transition losses apply only to the topside MOSFET(s),
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
an amount equal to ΔI
fective series resistance of C
charge or discharge C
signal that forces the regulator to adapt to the current
change and return V
this recovery time V
overshoot or ringing, which would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values. The availability of the I
not only allows optimization of control loop behavior, but
it also provides a DC coupled and AC fi ltered closed-loop
response test point. The DC step, rise time and settling
at this test point truly refl ects the closed-loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
APPLICATIONS INFORMATION
24
and become signifi cant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% effi ciency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
C
the switching frequency. A 25W supply will typically
require a minimum of 20μF to 40μF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. The
LTC3858-1 2-phase architecture typically halves this
input capacitance requirement over competing solu-
tions. Other losses including Schottky conduction losses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
IN
Transition Loss = (1.7) • V
has adequate charge storage and very low ESR at
OUT
OUT
OUT
LOAD
to its steady-state value. During
can be monitored for excessive
generating the feedback error
(ESR), where ESR is the ef-
OUT
IN
. ΔI
• 2 • I
LOAD
O(MAX)
also begins to
OUT
• C
shifts by
RSS
TH
• f
pin
can also be estimated by examining the rise time at the
pin. The I
circuit will provide an adequate starting point for most
applications.
The I
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I
give a sense of the overall loop stability without breaking
the feedback loop.
Placing a resistive load and a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the I
the feedback loop and is the fi ltered and compensated
control loop response.
The gain of the loop will be increased by increasing R
and the bandwidth of the loop will be increased by de-
creasing C
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
TH
OUT
series R
, causing a rapid drop in V
TH
C
. If R
external components shown in Figure 12
C
C
-C
is increased by the same factor that C
C
fi lter sets the dominant pole-zero
TH
TH
pin waveforms that will
pin signal which is in
OUT
. No regulator can
38581f
C
C