NT256D64S88B1G Nanya Technology, NT256D64S88B1G Datasheet

NT256D64S88B1G

Manufacturer Part Number

NT256D64S88B1G

Description

(NT256D64S88Bxx) 256MB DDR DIMM

Manufacturer

Nanya Technology

Datasheet

1.NT256D64S88B1G.pdf (28 pages)

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NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G

NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G

NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)

512MB, 256MB and 128MB

PC3200, PC2700 and PC2100

Unbuffered DDR DIMM

184 pin Unbuffered DDR DIMM

Based on DDR400/333/266 256M bit B Die device

Features

• 184 Dual In-Line Memory Module (DIMM)

• Unbuffered DDR DIMM based on 256M bit die B device,

organized as either 32Mbx8 or 16Mbx16

• Performance:

• Intended for 133, 166 and 200 MHz applications

• Inputs and outputs are SSTL-2 compatible

• V

• SDRAMs have 4 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

Description

NT512D64S8HB0G, NT512D64S8HB1G, NT512D64S8HB1GY, NT512D72S8PB0G, NT256D64SH88B0G, NT256D64SH88B1G,

NT256D64SH88B1GY, NT256D72S89B0G and NT128D64SH4B1G are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM

Dual In-Line Memory Modules (DIMM). NT512D64S8HB1GY and NT256D64SH88B1GY are packaged using lead free technology.

NT512D64S8HB0G, NT512D64S8HB1G and NT512D64S8HB1GY are 512MB modules organized as dual ranks using sixteen 32Mx8

TSOP devices. NT512D72S8PB0G has ECC and is organized as dual ranks using eighteen 32Mx8 TSOP devices. NT256D64SH88B0G,

NT256D64SH88B1G and NT256D64SH88B1GY are 256MB modules organized as single rank using eight 32Mx8 TSOP devices.

NT256D72S89B0G has ECC and is organized as single rank using nine 32Mx8 TSOP devices. NT128D64SH4B1G are 128MB modules,

organized as single rank using four 16Mx16 TSOP devices.

Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves

high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation

type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.

The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be

accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.

REV 2.2

Aug 3, 2004

Preliminary

DIMM CAS Latency

= V

Clock Frequency

Clock Cycle

DQ Burst Frequency

DDQ

Speed Sort

= 2.5V ± 0.2V (2.6V ± 0.1V for PC3200)

PC3200 PC2700 PC2100

200

400

166

333

2.5

75B

133

266

2.5

7.5

MHz

Unit

• DRAM DLL aligns DQ and DQS transitions with clock transitions

• Address and control signals are fully synchronous to positive

• Programmable Operation:

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 7.8 s Max. Average Periodic Refresh Interval

• Serial Presence Detect EEPROM

• Gold contacts

• SDRAMs are packaged in TSOP packages

• “Green” packaging – lead free

clock edge

- DIMM CAS Latency: 2, 2.5, 3

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

NANYA reserves the right to change products and specifications without notice.

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