NT256D72S89AKGU Nanya Technology, NT256D72S89AKGU Datasheet

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NT256D72S89AKGU

Manufacturer Part Number
NT256D72S89AKGU
Description
256MB DDR SDRAM DIMM
Manufacturer
Nanya Technology
Datasheet
NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
184pin Low Profile Registered DDR SDRAM MODULE
Features
• 32Mx72 Low Profile Registered DDR DIMM based on 32Mx8
• JEDEC Standard 184-pin Dual In-Line Memory Module
• Error Check Correction (ECC) Support
• Phase-lock loop (PLL) clock driver to reduce loading
• Registered inputs with one-clock delay
• Performance:
• Intended for 100 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
*
D escription
NT256D72S89AKGU is a Low Profile Registered 184-Pin 1U Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module
(DIMM), organized as a one-bank 32Mx72 high-speed memory array. The module uses nine 32Mx8 DDR SDRAMs in 400 mil TSOP II
packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these
common design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 133 MHz clock speeds and achieves high-speed data transfer rates of up to
266 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the
DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
O rdering Information
REV 1.1
12/2002
One clock cycle added for registered DIMMs to account for input register.
f
f
t
DDR SDRAM
DQ
CK
CK
NT256D72S89AKGU-7K
NT256D72S89AKGU-75B
NT256D72S89AKGU-8B
DD
DIMM CAS Latency
= 2.5Volt ± 0.2, V
Clock Frequency
Clock Cycle
DQ Burst Frequency
Part Number
Speed Sort
DDQ
*
= 2.5Volt ± 0.2
PC1600
-8B
100
200
10
133MHz (7.5ns @ CL= 2.5)
3
143MHz (7ns @ CL = 2.5)
125MHz (8ns @ CL = 2.5)
133MHz (7.5ns @ CL= 2)
100MHz (10ns @ CL = 2)
100MHz (10ns @ CL = 2)
-75B
133
266
3.5
7.5
PC2100
133
266
-7K
7.5
3
MHz
MHz
Unit
Speed
ns
DDR266A
DDR266B
DDR200
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
• Data is read or written on both clock edges
• Bi-directional data strobe with one clock cycle preamble and
• Address and control signals are fully synchronous to positive
• Programmable Operation:
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/1 Addressing (row/column/bank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
one-half clock post-amble
clock edge
- Device CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
PC2100
PC2100
PC1600
Based on 32Mx8 DDR SDRAM
Organization
32Mx72
© NANYA TECHNOLOGY CORP.
Leads
Gold
Power
2.5V

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NT256D72S89AKGU Summary of contents

Page 1

... One clock cycle added for registered DIMMs to account for input register. D escription NT256D72S89AKGU is a Low Profile Registered 184-Pin 1U Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank 32Mx72 high-speed memory array. The module uses nine 32Mx8 DDR SDRAMs in 400 mil TSOP II packages ...

Page 2

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Pin Description CK0, CK0 Differential Clock Inputs CKE0 Clock Enable RAS Row Address Strobe CAS Column Address Strobe WE Write Enable S0 Chip Selects A0-A9, A11, A12 Address Inputs A10/AP Address Input/Autoprecharge BA0, BA1 ...

Page 3

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Input/Output Functional Description Symbol Type Polarity Positive CK0 (SSTL) Edge Negative CK0 (SSTL) Edge Active CKE0 (SSTL) High Active S0 (SSTL) Low Active RAS CAS (SSTL) Low V Supply REF V Supply DDQ BA0, BA1 ...

Page 4

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Functional Block Diagram RS0 DQS0 DM0/DQS9 CS DM DQS DQ0 I/O 7 DQ1 I/O 6 DQ2 I/O 1 DQ3 I DQ4 I/O 5 DQ5 I/O 4 DQ6 I/O 3 DQ7 I/O 2 DQS1 DM1/DQS10 CS DM DQS DQ8 I/O 7 DQ9 I/O 6 DQ10 I DQ11 DQ12 I/O 5 DQ13 I/O 4 DQ14 I/O 3 DQ15 I/O 2 DQS2 ...

Page 5

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Serial Presence Detect -- Part 32Mx72 1 BANK REGISTERED DDR SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD Byte Description Number of Serial PD Bytes Written during 0 Production 1 Total Number of Bytes in Serial PD device ...

Page 6

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Serial Presence Detect -- Part 32Mx72 1 BANK REGISTERED DDR SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD Byte Description 64-71 Manufacturer’s JEDEC ID Code 72 Module Manufacturing Location 73-90 Module Part number ...

Page 7

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Absolute Maximum Ratings Symbol Voltage on I/O pins relative to Vss OUT Voltage on Input relative to Vss V IN Voltage on VDD supply relative to Vss V DD Voltage on VDDQ supply relative to Vss V DDQ Operating Temperature (Ambient Storage Temperature (Plastic) ...

Page 8

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM DC Electrical Characteristics and Operating Conditions ( ° ° 2.5V ± 0.2V; V DDQ DD Symbol V Supply Voltage DD V I/O Supply Voltage DDQ V V Supply Voltage, I/O Supply Voltage SS, SSQ V I/O Reference Voltage REF V I/O Termination Voltage (System Input High (Logic1) Voltage ...

Page 9

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced Tests for AC timing, I ...

Page 10

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Operating, Standby, and Refresh Currents ( ° ° 2.5V ± 0.2V; V DDQ DD Symbol Parameter/Condition Operating Current: one bank; active/precharge DQ, DM, and DQS inputs changing twice per clock cycle; address DD0 (MIN); and control inputs changing once per clock cycle Operating Current: one bank ...

Page 11

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module ( ° ° 2.5V ± 0.2V; V DDQ DD Symbol Parameter t DQ output access time from CK/ DQS output access time from CK/CK DQSCK t CK high-level width low-level width ...

Page 12

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module ( ° ° 2.5V ± 0.2V; V DDQ DD Symbol Parameter Address and control input setup time t IS (slow slewrate) t Input pulse width IPW t Read preamble RPRE ...

Page 13

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM AC Timing Specification Notes 1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/ REF 3. Inputs are not recognized as valid until V 4 ...

Page 14

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Package Dimensions 133.35 5.250 Θ 2.5 0.098 Detail A 1.80 0.071 Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) REV 1.1 12/2002 FRONT 131.35 5.171 128.95 5.077 Register PLL ...

Page 15

... NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Revision Log Rev Date 0.1 08/2002 Preliminary Release 0.2 09/2002 Added t (Power down exit time Timing Table PDEX 09/2002 Updated SPD Table bytes 27, 29, and 63 for DDR200 0.3 11/2002 Updated I currents in Operating, Standby, and Refresh Currents Table DD 1 ...

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