SC16C554DB NXP Semiconductors, SC16C554DB Datasheet - Page 10

• Manufacturer Part Number: SC16C554DB
• Description: 5 V 3.3 V and 2.5 V quad UART - 5 Mbit/s (max.) with 16-byte FIFOs
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 2:
9397 750 13133
Product data sheet
Symbol
D0 to D2,
D3 to D7
DSRA,
DSRB,
DSRC, DSRD
DTRA,
DTRB,
DTRC, DTRD
GND
INTA, INTB,
INTC, INTD
INTSEL
IOR
Pin description
Pin
PLCC68 LQFP64 LQFP80
66 to 68,
1 to 5
10, 26,
44, 60
12, 24,
46, 58
6, 23,
40, 57
15, 21,
49, 55
65
52
53 to 55,
56 to 60
1, 17,
32, 48
3, 15,
34, 46
14, 28,
45, 61
6, 12,
37, 43
-
40
…continued
7 to 9,
11 to 15
22, 39,
62, 79
24, 37,
64, 77
16, 36,
56, 76
27, 34,
67, 74
6
70
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Type
I/O
I
O
I
O
I
I
Rev. 01 — 9 February 2005
Description
Data bus (bi-directional). These pins are the 8-bit, 3-state data
bus for transferring information to or from the controlling CPU. D0 is
the least significant bit and the first data bit in a transmit or receive
serial data stream.
Data Set Ready (active LOW). These inputs are associated with
individual UART channels, A through D. A logic 0 on this pin
indicates the modem or data set is powered-on and is ready for data
exchange with the UART. This pin has no effect on the UART’s
transmit or receive operation.
Data Terminal Ready (active LOW). These outputs are associated
with individual UART channels, A through D. A logic 0 on this pin
indicates that the SC16C554B/554DB is powered-on and ready.
This pin can be controlled via the modem control register. Writing a
logic 1 to MCR[0] will set the DTR output to logic 0, enabling the
modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or
after a reset. This pin has no effect on the UART’s transmit or
receive operation.
Signal and power ground.
Interrupt A, B, C, D (active HIGH). This function is associated with
the 16 mode only. These pins provide individual channel interrupts
INTA to INTD. INTA to INTD are enabled when MCR[3] is set to a
logic 1, interrupts are enabled in the interrupt enable register (IER),
and when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty,
or when a modem status flag is detected. When the 68 mode is
selected, the functions of these pins are re-assigned. 68 mode
functions are described under their respective name/pin headings.
Interrupt Select (active HIGH, with internal pull-down). This
function is associated with the 16 mode only. When the 16 mode is
selected, this pin can be used in conjunction with MCR[3] to enable
or disable the 3-state interrupts, INTA to INTD, or override MCR[3]
and force continuous interrupts. Interrupt outputs are enabled
continuously by making this pin a logic 1. Making this pin a logic 0
allows MCR[3] to control the 3-state interrupt output. In this mode,
MCR[3] is set to a logic 1 to enable the 3-state outputs. This pin is
disabled in the 68 mode. Due to pin limitations on the 64-pin
packages, this pin is not available. To cover this limitation, the
SC16C554DBIB64 version operates in the continuous interrupt
enable mode by bonding this pin to V
SC16C554BIB64 operates with MCR[3] control by bonding this pin
to GND.
Input/Output Read strobe (active LOW). This function is
associated with the 16 mode only. A logic 0 transition on this pin will
load the contents of an internal register defined by address bits
A0 to A2 onto the SC16C554B/554DB data bus (D0 to D7) for
access by external CPU. This pin is disabled in the 68 mode.
SC16C554B/554DB
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
CC
internally. The
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