SC16C554DB NXP Semiconductors, SC16C554DB Datasheet - Page 28
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
SC16C554DB
Manufacturer Part Number
SC16C554DB
Description
5 V 3.3 V and 2.5 V quad UART - 5 Mbit/s (max.) with 16-byte FIFOs
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C554DB.pdf
(51 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC16C554DB
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
SC16C554DBIA68
Manufacturer:
NXP
Quantity:
116
Part Number:
SC16C554DBIA68
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Company:
Part Number:
SC16C554DBIA68,529
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
SC16C554DBIB64
Manufacturer:
NXP
Quantity:
595
Part Number:
SC16C554DBIB64
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
SC16C554DBIB64,128
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
SC16C554DBIB64,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
SC16C554DBIB64,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 13133
Product data sheet
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 15:
Bit
7
6
5
4
3
2
1:0
Line Control Register bits description
Symbol
LCR[7]
LCR[6]
LCR[5]
LCR[4]
LCR[3]
LCR[2]
LCR[1:0]
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Rev. 01 — 9 February 2005
Description
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
Set parity. If the parity bit is enabled, LCR[5] selects the forced parity
format. Programs the parity conditions (see
Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,
LCR[4] selects the even or odd parity format.
Parity enable. Parity or no parity can be selected via this bit.
Stop bits. The length of stop bit is specified by this bit in conjunction
with the programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 for alerting
the remote receiver to a line break condition.
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a
logical 1 for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a
logical 0 for the transmit and receive data.
Logic 0 = Odd Parity is generated by forcing an odd number of
logic 1s in the transmitted data. The receiver must be programmed
to check the same format (normal default condition).
Logic 1 = Even Parity is generated by forcing an even number of
logic 1s in the transmitted data. The receiver must be programmed
to check the same format.
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during the transmission, receiver
checks the data and parity for transmission errors.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
SC16C554B/554DB
Table
18).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
Table
17).
www.DataSheet4U.com
16).
28 of 51