SC16C752BIBS Philips Semiconductors, SC16C752BIBS Datasheet - Page 5

• Manufacturer Part Number: SC16C752BIBS
• Description: 5 V/ 3.3 V and 2.5 V dual UART/ 5 Mbit/s (max.)/ with 64-byte FIFOs
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 2:
9397 750 14443
Product data
Symbol
A0
A1
A2
CDA, CDB
CSA, CSB
CTSA,
CTSB
D0-D4,
D5-D7
DSRA,
DSRB
DTRA,
DTRB
GND
INTA, INTB
IOR
IOW
n.c.
Pin description
Pin
LQFP48 HVQFN32
28
27
26
40, 16
10, 11
38, 23
44-48,
1-3
39, 20
34, 35
17
30, 29
19
15
12, 24,
25, 37
5.2 Pin description
19
18
17
-
8, 9
25, 16
27-31, 32,
1-2
-
-
13
21, 20
14
12
-
Type
I
I
I
I
I
I
I/O
I
O
I
O
I
I
-
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Description
Address 0 select bit. Internal registers address selection.
Address 1 select bit. Internal registers address selection.
Address 2 select bit. Internal registers address selection.
Carrier Detect (Active-LOW). These inputs are associated with individual
UART channels A and B. A logic LOW on these pins indicates that a carrier
has been detected by the modem for that channel. The state of these inputs
is reflected in the modem status register (MSR).
Chip Select (Active-LOW). These pins enable data transfers between the
user CPU and the SC16C752B for the channel(s) addressed. Individual
UART sections (A, B) are addressed by providing a logic LOW on the
respective CSA and CSB pins.
Clear to Send (Active-LOW). These inputs are associated with individual
UART channels A and B. A logic 0 (LOW) on the CTS pins indicates the
modem or data set is ready to accept transmit data from the SC16C752B.
Status can be tested by reading MSR[4]. These pins only affect the transmit
and receive operations when Auto-CTS function is enabled via the Enhanced
Feature Register EFR[7] for hardware flow control operation.
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data stream.
Data Set Ready (Active-LOW). These inputs are associated with individual
UART channels A and B. A logic 0 (LOW) on these pins indicates the modem
or data set is powered-on and is ready for data exchange with the UART. The
state of these inputs is reflected in the modem status register (MSR).
Data Terminal Ready (Active-LOW). These outputs are associated with
individual UART channels A and B. A logic 0 (LOW) on these pins indicates
that the SC16C752B is powered-on and ready. These pins can be controlled
via the modem control register. Writing a logic 1 to MCR[0] will set the DTR
output to logic 0 (LOW), enabling the modem. The output of these pins will
be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
Signal and power ground.
Interrupt A and B (Active-HIGH). These pins provide individual channel
interrupts INTA and INTB. INTA and INTB are enabled when MCR[3] is set to
a logic 1, interrupt sources are enabled in the interrupt enable register (IER).
Interrupt conditions include: receiver errors, available receiver buffer data,
available transmit buffer space, or when a modem status flag is detected.
INTA, INTB are in the high-impedance state after reset.
Input/Output Read strobe (Active-LOW). A HIGH-to-LOW transition on
IOR will load the contents of an internal register defined by address bits
A0-A2 onto the SC16C752B data bus (D0-D7) for access by external CPU.
Input/Output Write strobe (Active-LOW). A LOW-to-HIGH transition on
IOW will transfer the contents of the data bus (D0-D7) from the external CPU
to an internal register that is defined by address bits A0-A2 and CSA and
CSB.
Not connected.
Rev. 03 — 14 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C752B
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