SC16IS762 Philips Semiconductors, SC16IS762 Datasheet - Page 33

• Manufacturer Part Number: SC16IS762
• Description: (SC16IS752 / SC16IS762) Dual UART
• Manufacturer: Philips Semiconductors

NXP Semiconductors
9. RS-485 features
SC16IS752_SC16IS762_6
Product data sheet
8.21 Enhanced Features Register (EFR)
9.1 Auto RS-485 RTS control
9.2 RS-485 RTS output inversion
This 8-bit register enables or disables the enhanced features of the UART.
the Enhanced Features Register bit settings.
Table 31.
Normally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the
logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR
register bit 4 will take the precedence over the other two modes; once this bit is set, the
transmitter will control the state of the RTS pin. The transmitter automatically asserts the
RTS pin (logic 0) once the host writes data to the transmit FIFO, and deasserts RTS pin
(logic 1) once the last bit of the data has been transmitted.
To use the auto RS-485 RTS mode the software would have to disable the hardware flow
control function.
EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.
When the transmitter has data to be sent it deasserts the RTS pin (logic 1), and when the
last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).
Bit
7
6
5
4
3:0
Symbol
EFR[7]
EFR[6]
EFR[5]
EFR[4]
EFR[3:0]
Enhanced Features Register bits description
Rev. 06 — 19 December 2006
Dual UART with I
Description
CTS flow control enable.
RTS flow control enable.
Special character detect.
Enhanced functions enable bit.
Combinations of software flow control can be selected by programming
these bits. See
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a
HIGH signal is detected on the CTS pin.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when
the receiver FIFO halt trigger level TCR[3:0] is reached, and goes
LOW when the receiver FIFO resume transmission trigger level
TCR[7:4] is reached.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. Received data is compared
with Xoff2 data. If a match occurs, the received data is transferred to
FIFO and IIR[4] is set to a logical 1 to indicate a special character has
been detected.
logic 0 = disables enhanced functions and writing to IER[7:4],
FCR[5:4], MCR[7:5].
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and
MCR[7:5] so that they can be modified.
Table 3 “Software flow control options
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
© NXP B.V. 2006. All rights reserved.
(EFR[3:0])”.
Table 31
shows
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