SC16IS762 Philips Semiconductors, SC16IS762 Datasheet - Page 40

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SC16IS762

Manufacturer Part Number
SC16IS762
Description
(SC16IS752 / SC16IS762) Dual UART
Manufacturer
Philips Semiconductors
Datasheet

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NXP Semiconductors
SC16IS752_SC16IS762_6
Product data sheet
Fig 18. Master writes to slave
Fig 19. Master read from slave
(1) See
(1) See
S
White block: host to SC16IS752/SC16IS762
Grey block: SC16IS752/SC16IS762 to host
White block: host to SC16IS752/SC16IS762
Grey block: SC16IS752/SC16IS762 to host
Table 33
Table 33
SLAVE ADDRESS
S
for additional information.
for additional information.
SLAVE ADDRESS
The register read cycle (see
sending a slave address with the direction bit set to WRITE with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a Repeated
START followed again by the device address, but this time with the direction bit set to
READ. The data bytes starting at the internal subaddress will be clocked out of the device,
each followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated
by a STOP signal.
Table 33.
Bit
7
6:3
2:1
0
W
Register address byte (I
Name
-
A[3:0]
CH1, CH0
-
A
W
REGISTER ADDRESS
Rev. 06 — 19 December 2006
Dual UART with I
A
REGISTER ADDRESS
Figure
Function
not used
UART’s internal register select
Channel select.
not used
00 = channel A
01 = channel B
10 = reserved
11 = reserved
2
(1)
C)
19) commences in a similar manner, with the master
A
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
nDATA
(1)
S
A
SLAVE ADDRESS
A
nDATA
LAST DATA
A
002aab047
R
© NXP B.V. 2006. All rights reserved.
P
NA
A
002aab048
P
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