MBM29SL800BD Fujitsu Media Devices, MBM29SL800BD Datasheet - Page 22

• Manufacturer Part Number: MBM29SL800BD
• Description: (MBM29SL800TD/BD) FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT
• Manufacturer: Fujitsu Media Devices

22
MBM29SL800TD
RY/BY
Ready/Busy
Byte/Word Configuration
Data Protection
Write Pulse “Glitch” Protection
Logical Inhibit
Power-Up Write Inhibit
Sector Protection
The MBM29SL800TD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any
read/write or erase operation. If the MBM29SL800TD/BD are placed in an Erase Suspend mode, the RY/BY
output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to “(8) RY/BY Timing Diagram during Program/Erase Operation
Timing Diagram” and “(9) RESET, RY/BY Timing Diagram” in TIMING DIAGRAM for a detailed timing diagram.
The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to V
be connected to the host system via more than one RY/BY pin in parallel.
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29SL800TD/BD devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to “(10) Timing Diagram for Word Mode Configuration” and “(11) Timing Diagram for Byte Mode Configuration”
and “(12) BYTE Timing Diagram for Write Operations” in TIMING DIAGRAM for the timing diagram.
The MBM29SL800TD/BD are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices automat-
ically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of
the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE
must be a logical zero while OE is a logical one.
Power-up of the devices with WE
The internal state machine is automatically reset to the read mode on power-up.
Device user is able to protect each sector individually to store and protect data. Protection circuit voids both
program and erase commands that are addressd to protected sectors.
Any commands to program or erase addressed to protected sector are ignored (see “Sector Protection” in
FUNCTIONAL DESCRIPTION) .
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
-10/12
CE
8
to DQ
V
/MBM29SL800BD
IL
and OE
14
V
bits are tri-stated. However, the command bus cycle is always
IL
, CE
V
IH
V
will not accept commands on the rising edge of WE.
0
IH
to DQ
, or WE
7
and the DQ
V
IH
. To initiate a write cycle CE and WE
8
to DQ
-10/12
CC
; multiples of devices may
15
bits are ignored. Refer
CC
power-up
15
/A-
1
pin
0