cy27ee16 Cypress Semiconductor Corporation., cy27ee16 Datasheet - Page 4

• Manufacturer Part Number: cy27ee16
• Description: 1 Pll In-system Programmable Clock Generator With Individual 16k Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07440 Rev. *C
Table 1. Summary Table – CY27EE16ZE Programmable Registers
CY27EE16ZE Frequency Calculation and
Register Definitions
The CY27EE16ZE is an extremely flexible clock generator
with four basic variables that can be used to determine the final
output frequency. They are the input reference frequency
(REF), the internally calculated P and Q dividers, and the post
divider, which can be a fixed or calculated value. There are
three basic formulas for determining the final output frequency
of a CY27EE16ZE-based design. Any one of these three
formulas may be used:
Register Description
09H
OCH
10H
11H
12H
13H
14H
40H
41H
42H
44H
45H
46H
47H
CLKOE control
DIV1SRC mux and
DIV1N divider
Input Pin Control
Registers
Write Protect
Registers
Input crystal oscillator
drive control
Input load capacitor
control
ADC Register
Charge Pump and PB
counter
PO counter, Q
counter
Crosspoint switch
matrix control
DIV2SRC mux and
DIV2N divider
D7
CLKSRC2
CLKSRC0
CLKSRC1
DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)
DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)
default=0
CLOCK1
CLOCK3
CLOCK5
drSrc(1)
ADCEn-
Load(7)
FTAAd-
OESrc
PB(7)
Cap-
able
PO
for
for
for
0
1
D6
CLKSRC1
CLKSRC2
CLKSRC0
OE0PadS
default=0
CLOCK6
CBypCnt
CLOCK1
CLOCK4
CLOCK5
drSrc(0)
FTAAd-
Load(6)
PB(6)
Cap-
el[1]
Q(6)
AD-
for
for
for
1
D5
CLKSRC0
CLKSRC1
CLKSRC2
OE0PadS
default=1
CLOCK5
XCapSrc
CLOCK1
CLOCK4
CLOCK6
Load(5)
Cnt[2]
PB(5)
ADC-
Cap-
Q(5)
el[0]
for
for
for
0
CLK = ((REF * P)/Q)/Post Divider
CLK = REF/Post Divider
CLK = REF
The basic PLL block diagram is shown in Figure 2. Each of the
six clock outputs on the CY27EE16ZE has a total of seven
output options available to it. There are six post divider options
available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N
and DIV2N are independently calculated and are applied to
individual output groups. The post divider options can be
applied to the calculated VCO frequency ((REF*P)/Q) or to the
reference frequency directly.
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the reference frequency
directly to the crosspoint switch matrix.
D4
CLKSRC2
CLKSRC0
CLKSRC1
OE1PadS
XDRV(1)
CLOCK2
CLOCK4
CLOCK6
MemWP
Pump(2)
Load(4)
Cnt[1]
PB(4)
ADC-
Cap-
Q(4)
el[1]
for
for
for
0
D3
CLKSRC1
CLKSRC0
OE1PadS
CLOCK4
XDRV(0)
CLOCK2
CLOCK6
Pump(1)
Load(3)
WPSrc
Cnt[0]
PB(3)
ADC-
Cap-
Q(3)
el[0]
for
for
1
D2
ADCFilt[1] ADCFilt[0]
CLKSRC0
PDMEna-
CLOCK3
CLOCK2
Pump(0)
WPPad-
Load(2)
Sel[2]
PB(2)
Cap-
Q(2)
ble
for
0
1
1
CY27EE16ZE
D1
CLKSRC2
PDMPad-
CLOCK2
CLOCK3
WPPad-
Load(1)
Sel[1]
Sel[1]
PB(9)
PB(1)
Cap-
Q(1)
for
0
1
1
Page 4 of 17
D0
CLKSRC1
CLKSRC2
PDMPad-
CLOCK1
CLOCK3
CLOCK5
WPPad-
Load(0)
Sel[0]
Sel[0]
PB(8)
PB(0)
Cap-
Q(0)
for
for
0
0
1
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