cy27ee16 Cypress Semiconductor Corporation., cy27ee16 Datasheet - Page 8

• Manufacturer Part Number: cy27ee16
• Description: 1 Pll In-system Programmable Clock Generator With Individual 16k Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07440 Rev. *C
Table 8. PLL Post Divider Options
PLL Post Divider Options
The output of the VCO is routed through two independent
muxes, then to two divider banks to determine the final clock
output frequency. The mux determines if the clock signal
feeding into the divider banks is the calculated VCO frequency
or REF. There are 2 select muxes (DIV1SRC and DIV2SRC)
and 2 divider banks (Divider Bank 1 and Divider Bank 2) used
to determine this clock signal. The clock signals passing
through DIV1SRC and DIV2SRC are referred to as DIV1CLK
and DIV2CLK, respectively.
The divider banks have 4 unique divider options available: /2,
/3, /4, and /DIVxN. DIVxN is a variable that can be indepen-
dently programmed (DIV1N and DIV2N) for each of the 2
divider banks. The minimum value of DIVxN is 4. The
maximum value of DIVxN is 127. A value of DIVxN below 4 is
not guaranteed to work properly.
DIV1SRC is a single bit variable, controlled by register OCH.
The remaining 7 bits of register OCH determine the value of
post divider DIV1N.
DIV2SRC is a single bit variable, controlled by register 47H.
The remaining 7 bits of register 47H determine the value of
post divider DIV2N.
Register OCH and 47H are defined in Table 8.
Charge Pump Settings [40H(2..0)]
The correct pump setting is important for PLL stability. Charge
pump settings are controlled by bits (4..2) of register 40H, and
Table 10.Register 40H Change Pump Bit Settings
Address
Address
OCH
47H
40H
DIV1SRC
DIV2SRC
D7
D7
1
DIV1N(6)
DIV2N(6)
D6
D6
1
DIV1N(5)
DIV2N(5)
D5
D5
0
DIV1N(4)
DIV2N(4)
Pump(2)
D4
D4
are dependent on internal variable PB (see section "[00H to
08H] – Reserved [0AH to 0BH] – Reserved [0DH to 0FH]
–Reserved [15H to 3FH] –Reserved [43H] –Reserved [48H to
FFH] –Reserved", page 9). Table 9 summarizes the proper
charge pump settings, based on P
40H Change Pump Bit Settings", page 8, for register 40H bit
locations.
Although using Table 10 will guarantee stability, it is recom-
mended to use the Print Preview function in CyberClocks™ to
determine the ideal charge pump settings for optimal jitter
performance.
PLL stability cannot be guaranteed for P
and above 1023. If P
CyberClocks to determine the best charge pump setting.
Table 9. Charge Pump Settings
Charge Pump Setting
– Pump(2..0)
101, 110, 111
DIV1N(3)
DIV2N(3)
Pump(1)
D3
000
001
010
011
100
D3
total
DIV1N(2)
DIV2N(2)
Pump(0)
D2
D2
values above 1023 are needed, use
Do Not Use – device will be unstable
total
Calculated P
DIV1N(1)
DIV2N(1)
. See Table 10, "Register
800 – 1023
PB(9)
CY27EE16ZE
480 – 639
640 – 799
45 – 479
D1
D1
16 – 44
total
values below 16
total
Page 8 of 17
DIV1N(0)
DIV2N(0)
PB(8)
D0
D0
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