cy27ee16 Cypress Semiconductor Corporation., cy27ee16 Datasheet - Page 7

• Manufacturer Part Number: cy27ee16
• Description: 1 Pll In-system Programmable Clock Generator With Individual 16k Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07440 Rev. *C
Power-down Mode (PDM) and Output Enable
(OE) Registers for Pin 10
In the default clock configuration, pin 10 is configured as OE,
and not configured as PDM. As such, the Power-down mode
is not available unless the clock core is modified.
To Configure for PDM
To configure pin 10 for PDM, use the SPI to write the following:
Now, when the PDM signal (an active LOW signal) is asserted,
all of the clock components are shut down and the part enters
a low-power state.
The serial port and EE blocks will still be available. These
circuits automatically go into a low-power state when not being
used, but will draw power when active.
Note: For default factory programmed devices, Register
40H[7:6] may be programmed to 00. In this case Register
40H[7:6] must be programmed to 11 in order for clock outputs
to be enabled.
To Configure for OE
To reconfigure pin 10 as OE again, so that pin 10 controls
enable/disable of the output divider bank, use the SPI to write
the following:
Write Protect (WP) Registers
To reconfigure pin 17 as WP, to control enable/disable of write
protection, use the SPI to write the following:
WPSrc, Register 11H[3] = 0
WPPadSel[2:0], Register 11H[2:0] = 100
Table 6. Q Counter Register Definition
Table 7. P Counter Register Definition
1. PDMEnable, Register 10H[2] = 1
2. PDMPadSel[1:0], Register 10H[1:0] =10
3. OESrc, Register 10H[7] = 1 (to redirect control of output
1. OESrc, Register 10H[7] = 0
2. OE0PadSel[1:0], Register 10H[6:5] =10
3. OE1PadSel[1:0], Register 10H[4:3] =10
4. PDMEnable, Register 10H[2] = 0
5. Mem WP, Register 11H[4] = 0
6. WPSrc, Register 11H[3] = 1
Register
Address
enable to memory, register 40H[7:6], and thereby enable
both divider banks).
40H
41H
42H
42H
PB(7)
PO
PO
D7
D7
1
PB(6)
Q(6)
Q(6)
D6
D6
1
PB(5)
Q(5)
Q(5)
D5
D5
0
Pump(2)
PB(4)
Q(4)
Q(4)
D4
D4
When active (WP = 1), WP prevents the control logic for the
EE from initiating a erase/program cycle for any of the
EEPROM blocks (16-Kbit scratchpad and clock configuration
block). All serial shifting works as normal.
PLL Frequency, Q Counter
The first counter is known as the Q counter. The Q counter
divides REF by its calculated value. Q is a 7 bit divider with a
maximum value of 127 and minimum value of 0. The primary
value of Q is determined by 7 bits in register 42H (6..0), but 2
is added to this register value to achieve the total Q, or Q
Q
Q
The minimum value of Q
is 129. Register 42H is defined in Table 6.
Stable operation of the CY27EE16ZE cannot be guaranteed if
REF/Q
are defined in Table 6.
PLL Frequency, P Counter
The next counter definition is the P (product) counter. The P
counter is multiplied with the (REF/Q
VCO frequency. The product counter, defined as P
made up of two internal variables, PB and PO. The formula for
calculating P
P
PB is a 10-bit variable, defined by registers 40H(1:0) and
41H(7:0). The 2 LSBs of register 40H are the two MSBs of
variable PB. Bits 4..2 of register 40H are used to determine the
charge pump settings (see section, "Charge Pump Settings
[40H(2..0)]", page 8”). The 3 MSBs of register 40H are preset
and reserved and cannot be changed.
PO is a single bit variable, defined in register 42H(7). This
allows for odd numbers in P
The remaining 7 bits of 42H are used to define the Q counter,
as shown in Table 6.
The minimum value of P
is 2055. To achieve the minimum value of P
should both be programmed to 0. To achieve the maximum
value of P
should be programmed to 1.
Stable operation of the CY27EE16ZE cannot be guaranteed if
the value of (P
100 MHz. Registers 40H, 41H and 42H are defined in Table 7.
total
total
total
is defined by the formula:
= (2(PB + 4) + PO)
= Q + 2.
total
Pump(1)
PB(3)
Q(3)
Q(3)
D3
D3
total
falls below 250 kHz. Q
total
, PB should be programmed to 1023, and PO
total
is:
*(REF/Q
Pump(0)
PB(2)
Q(2)
Q(2)
total
total
D2
D2
total
total
is 2. The maximum value of Q
is 8. The maximum value of P
)) is above 400 MHz or below
.
total
total
PB(9)
PB(1)
bit locations and values
Q(1)
CY27EE16ZE
Q(1)
D1
D1
) value to achieve the
total
Page 7 of 17
, PB and PO
PB(8)
PB(0)
Q(0)
Q(0)
D0
D0
total
total
total
, is
total
.
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