cy28551-3 Cypress Semiconductor Corporation., cy28551-3 Datasheet - Page 16

• Manufacturer Part Number: cy28551-3
• Description: Universal Clock Generator For Intel, Via And Sis
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-05677 Rev. *D
stopped CPU clock is Low due to tristate, both CPUT and
CPUC outputs will not be driven.
PU_STP# De-Assertion
The de-assertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the de-assertion to
active outputs is between 2-6 CPU clock periods (2 clocks are
shown). If the control register tristate bit corresponding to the
output of interest is programmed to '1', then the stopped CPU
outputs will be driven high within 10ns of CPU_Stop#
de-assertion to a voltage greater than 200mV
C P U C , 1 3 3 M H z
C P U T , 1 3 3 M H z
C P U C , 1 3 3 M H z
S R C C 1 0 0 M H z
S R C T 1 0 0 M H z
C P U T , 1 3 3 M H z
S R C C 1 0 0 M H z
S R C T 1 0 0 M H z
U S B , 4 8 M H z
U S B , 4 8 M H z
P C I, 3 3 M H z
P C I, 3 3 M H z
D O T 9 6 C
D O T 9 6 T
D O T 9 6 C
D O T 9 6 T
L I N K
R E F
R E F
L IN K
P D
P D
Figure 5. PD Deassertion Timing Waveform
Figure 4. PD Assertion Timing Waveform
< 3 0 0 µ s , > 2 0 0 m V
T d r iv e _ P W R D N #
< 1 .8 m s
T s ta b le
PCI_STP# Clarification
The PCI_STP# signal is an active low input used for cleanly
stopping and starting the PCI and PCIEX outputs while the rest
of the clock generator continues to function. The PCIF and
PCIEX clocks are special in that they can be programmed to
ignore PCI_STP# by setting the register bit corresponding to
the output of interest to free running. Outputs set to free
running will ignore both the PCI_STP# pin.
PCI_STP# Assertion
The impact of asserting the PCI_STP# signal will be the
following. The clock chip is to sample the PCI_STP# signal on
a rising edge of PCIF clock. After detecting the PCI_STP#
assertion low, all PCI and stoppable PCIF clocks will latch low
CY28551-3
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