cy28551-3 Cypress Semiconductor Corporation., cy28551-3 Datasheet - Page 17

• Manufacturer Part Number: cy28551-3
• Description: Universal Clock Generator For Intel, Via And Sis
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-05677 Rev. *D
on their next high to low transition. After the PCI clocks are
latched low, the stoppable PCIEX clocks will latch to low due
to tristate as show below. The one PCI clock latency as shown
is critical to system functionality, any violation of this may result
in system failure. The Tsu_pci_stp# is the setup time required
by the clock generator to correctly sample the PCI_STP#
assertion, this time is 10 ns minimum.
PCI_STP# De-Assertion
The de-assertion of the PCI_STP# signal is to function as
follows. The de-assertion of the PCI_STP# signal is to be
sampled on the rising edge of the PCIF free running clock
domain. After detecting PCI_STP# de-assertion, all PCI,
stoppable PCIF and Stoppable PCIEX clocks will resume in a
glitch free manner. The PCI and PCIEX clock resume latency
should exactly match the 1 PCI clock latency required for
PCI_STP# entry. The stoppable PCIEX clocks must be driven
high within 15ns of PCI_STP# de-assertion. The drawing
below shows the appropriate relationship. The Tsu_cpu_stp#
is the setup time required by the clock generator to correctly
sample the PCI_STP# de-assertion, this time is 10 ns
minimum.
CLKREQ# Clarification
The CLKREQ# signals are active low input used for clean
stopping and starting selected SRC outputs. The outputs
controlled by CLKREQ# are determined by the settings in
register bytes 10 and 11. The CLKREQ# signal is a
C P U T In t e r n a l
C P U C In t e r n a l
C P U _ S T P #
CPU_STP#
C P U T
C P U C
CPUT
CPUC
Figure 6. CPU_STP# Assertion Timing waveform
Figure 7. CPU_STP# De-Assertion
T d r iv e _ C P U _ S T P # , 1 0 n S > 2 0 0 m V
de-bounced signal in that its state must remain unchanged
during two consecutive rising edges of DIFC to be recognized
as a valid assertion or de-assertion. (The assertion and
de-assertion of this signal is absolutely asynchronous)
CLKREQ# Assertion
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the de-assertion to active outputs is between 2-6 PCIEX clock
periods (2 clocks are shown) with all CLKREQ# outputs
resuming simultaneously. If the CLKREQ# drive mode is
tristate, the all stopped PCIEX outputs must be driven high
within 10 ns of CLKREQ# de-assertion to a voltage greater
than 200mV
CLKREQ# De-Assertion
The impact of asserting the CLKREQ# pins is all DIF outputs
that are set in the control registers to stoppable via assertion
of CLKREQ# are to be stopped after their next transition.
When the control register CLKREQ# drive mode bit is
programmed to '0', the final state of all stopped PCIEX signals
is PCIEXT clock = High and PCIEXC = Low. There is to be no
change to the output drive current values, SRCT will be driven
high with a current value equal 6 x Iref, When the control
register CLKREQ# drive mode bit is programmed to '1', the
final state of all stopped DIF signals is low, both PCIEXT clock
and PCIEXC clock outputs will not be driven.
CY28551-3
Page 17 of 29
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