cy28551-3 Cypress Semiconductor Corporation., cy28551-3 Datasheet - Page 4

• Manufacturer Part Number: cy28551-3
• Description: Universal Clock Generator For Intel, Via And Sis
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-05677 Rev. *D
Pin Description
Frequency Select Pins (FS[D:A])
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C, and FS_D
inputs prior to VTT_PWRGD# assertion (as seen by the clock
synthesizer). Upon VTT_PWRGD# being sampled LOW by
the clock chip (indicating processor VTT voltage is stable), the
clock chip samples the FS_A, FS_B, FS_C, and FS_D input
values. For all logic levels of FS_A, FS_B, FS_C, FS_D and
FS_E, VTT_PWRGD# employs a one-shot functionality in that
once a valid LOW on VTT_PWRGD# has been sampled, all
further VTT_PWRGD#, FS_A, FS_B, FS_C, and FS_D transi-
tions will be ignored, except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
53
54
55
56
FSEL3 FSEL2 FSEL1 FSEL0
Pin No.
FSD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FSC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
**FSA/PCI2
*FSB/PCI3
VDDPCI
*SELP4_K8/PCI3
FSB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
(continued)
Name
FSA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
266.667 266.667
133.333 133.333
166.667 166.667
333.333 333.333
266.667 266.667
133.333 133.333
166.667 166.667
333.333 333.333
CPU0
200
100
400
200
200
100
400
200
I/O, PD 3.3V-tolerant input for CPU frequency selection/33-MHz clock output. Internal 150k
I/O, PU 3.3V-tolerant input for CPU frequency selection/33-MHz clock output. Internal 150k
I/O, PU 3.3V-tolerant input for CPU clock output buffer type selection/33-MHz clock output.
PWR 3.3V power supply for outputs.
Type
Figure 1. CPU and SRC Frequency Select Tables
CPU1
200
100
400
250
200
100
400
250
pull-down
Intel Type-3A output buffer
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
pull-up
Intel Type-3A output buffer
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
Internal 150k pull-up
Intel Type-3A output buffer
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
0 = K8 CPU buffer type, 1=P4 CPU buffer type.
SRC
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
66.6667 33.3333
66.6667 33.3333
66.6667 33.3333
66.6667 33.3333 666.67
66.6667 33.3333 666.67
66.6667 33.3333
66.6667 33.3333
66.6667 33.3333 1000
133.333 33.3333
133.333 33.3333
133.333 33.3333
133.333 33.3333 666.67
133.333 33.3333 666.67
133.333 33.3333
133.333 33.3333
133.333 33.3333 1000
LINK
PCI
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
CPU
VCO
800
800
800
800
800
800
800
800
800
800
Frequency Table (ROM)
Constant
CPU PLL
Gear
120
120
120
120
(G)
80
40
60
60
30
60
80
40
60
60
30
60
Description
CPU
60
60
60
63
63
60
60
60
60
60
60
63
63
60
60
60
M
CPU
200
200
200
175
175
200
200
250
200
200
200
175
175
200
200
250
N
PCIE
VCO
800
800
800
800
800
800
800
800
800
800
800
800
800
800
800
800
SRC PLL
Constant
Gear
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
CY28551-3
PCIE
Page 4 of 29
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
M
PCIE
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
N
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