ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 110
ds2156gn
Manufacturer Part Number
ds2156gn
Description
Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS2156GN.pdf
(265 pages)
- Current page: 110 of 265
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Channels 25 to 32 Channel Blocking Control Bits (CH25 to CH32)
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
CH16
CH24
CH32
CH8
7
7
7
7
0
0
0
0
CH15
CH23
CH31
CH7
TCBR1
Transmit Channel Blocking Register 1
8Ch
TCBR2
Transmit Channel Blocking Register 2
8Dh
TCBR3
Transmit Channel Blocking Register 3
8Eh
TCBR4
Transmit Channel Blocking Register 4
8Fh
6
0
6
0
6
0
6
0
CH14
CH22
CH30
CH6
5
0
5
0
5
0
5
0
CH13
CH21
CH29
CH5
4
0
4
0
4
0
4
0
110 of 265
CH12
CH20
CH28
CH4
3
0
3
0
3
0
3
0
CH11
CH19
CH27
CH3
2
0
2
0
2
0
2
0
CH18
CH26
CH10
CH2
1
0
1
0
1
0
1
0
CH17
CH25
CH1
CH9
0
0
0
0
0
0
0
0
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