ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 236

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Figure 34-5. Receive-Side 2.048MHz Boundary Timing (with Elastic Store
Enabled)
Note 1: RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1.
Note 2: RSYNC is in the output mode (IOCR1.4 = 0).
Note 3: RSYNC is in the input mode (IOCR1.4 = 1).
Note 4: RCHBLK is forced to 1 in the same channels as RSER (see Note 1).
Note 5: The F-bit position is passed through the receive-side elastic store.
Figure 34-6. Transmit-Side D4 Timing
Note 1: TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.1 = 0).
Note 2: TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.1 = 1).
Note 3: TSYNC in the multiframe mode (IOCR1.2 = 1).
Note 4: TLINK data (Fs bits) is sampled during the F-bit position of even frames for insertion into the outgoing T1 stream when enabled through
FRAME#
TSSYNC
TSYNC
TSYNC
TSYNC
TLINK
TLCLK
T1TCR1.2.
RCHBLK
RSYSCLK
RMSYNC
RCHCLK
RSYNC
RSYNC
RSER
RSIG
2
3
4
1
3
2
4
1
1
2
CHANNEL 31
3
A
CHANNEL 31
4
B
5
C/A D/B
LSB MSB
6
7
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8
CHANNEL 32
9
10
A
CHANNEL 32
11
B
C/A D/B
12
LSB
1
2
CHANNEL 1
3
CHANNEL 1
4
5