ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 144
![no-image](/images/no-image-200.jpg)
ds2156gn
Manufacturer Part Number
ds2156gn
Description
Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS2156GN.pdf
(265 pages)
- Current page: 144 of 265
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of
the receive FIFO.
Bit 3/Receive FIFO Empty (REMPTY). A real-time bit that is set high when the receive FIFO is empty.
Bit 4/Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 5/Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/HDLC #1 Opening Byte Event (H1OBT). Set when the next byte available in the receive FIFO is the first
byte of a message.
Bit 1/HDLC #1 Transmit FIFO Underrun Event (H1UDR). Set when the transmit FIFO empties out without
having seen the TMEND bit set. An abort is automatically sent. This bit is latched and is cleared when read.
Bit 2/HDLC #2 Opening Byte Event (H2OBT). Set when the next byte available in the receive FIFO is the first
byte of a message.
Bit 3/HDLC #2 Transmit FIFO Underrun Event (H2UDR). Set when the transmit FIFO empties out without
having seen the TMEND bit set. An abort is automatically sent. This bit is latched and is cleared when read
PS2
0
0
0
0
1
PS1
0
0
1
1
0
—
7
0
—
7
0
PS0
0
1
0
1
0
—
6
0
INFO5, INFO6
HDLC #1 Information Register
HDLC #2 Information Register
2Eh, 2Fh
INFO4
HDLC Event Information Register #4
2Dh
—
6
0
In Progress
Packet OK: Packet ended with correct CRC codeword
CRC Error: A closing flag was detected, preceded by a corrupt CRC
codeword
Abort: Packet ended because an abort signal was detected (seven or
more 1s in a row).
Overrun: HDLC controller terminated reception of packet because
receive FIFO is full.
TEMPTY
—
5
0
5
0
—
TFULL
4
0
4
0
144 of 265
Packet Status
H2UDR
REMPTY
3
0
3
0
H2OBT
2
0
PS2
2
0
H1UDR
1
0
PS1
1
0
H1OBT
0
0
PS0
0
0
.
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