cef830g Hope Microelectronics co., Ltd, cef830g Datasheet - Page 65
cef830g
Manufacturer Part Number
cef830g
Description
Rf42/43 Ism Transmitter
Manufacturer
Hope Microelectronics co., Ltd
Datasheet
1.CEF830G.pdf
(113 pages)
- Current page: 65 of 113
- Download datasheet (4Mb)
Register 0Ah. Microcontroller Output Clock
Reset value = xx000110
Name
Type
Bit
Bit
7:6
5:4
2:0
3
Tel: +86-755-82973805
D7
mclk[2:0]
Reserved
clkt[1:0]
Name
enlfc
Reserved
R
D6
Reserved.
Clock Tail.
If enlfc = 0 then it can be useful to provide a few extra cycles for the
microcontroller to complete its operation. Setting the clkt[1:0] register will
provide the addition cycles of the clock before it shuts off.
00:
01:
10:
11:
Enable Low Frequency Clock.
When enlfc = 1 and the chip is in Sleep mode then the 32.768 kHz clock will be
provided to the microcontroller no matter what the selection of mclk[2:0] is. For
example if mclk[2:0] = ‗000‘, 30 MHz will be available through the GPIO to
output to the microcontroller in all Idle or TX states. When the chip is
commanded to Sleep mode the 30 MHz clock will become 32.768 kHz.
Microcontroller Clock.
Different clock frequencies may be selected for configurable GPIO clock
output. All clock frequencies are created by dividing the XTAL except for the 32
kHz clock which comes directly from the 32 kHz RC Oscillator. The mclk[2:0]
setting is only valid when xton = 1 except the 111.
000:
001:
010:
011:
100:
101:
110:
111:
Fax: +86-755-82973550
0 cycle
128 cycles
256 cycles
512 cycles
D5
30 MHz
15 MHz
10 MHz
4 MHz
3 MHz
2 MHz
1 MHz
32.768 kHz
clkt[1:0]
R/
w
D4
E-mail: sales@hoperf.com
enlfc
Function
D3
R/
w
D2
R F 4 2 / 4 3
http://www.hoperf.com
mclk[2:0]
D1
R/
w
D0
65
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